summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-11-10rockchip: make_fit_atf.py: allow inclusion of a tee binaryHeiko Stuebner
A trusted execution environment should also get loaded as loadable from a fit image, so add the possibility to present a tee.elf to make_fit_atf.py that then gets included as additional loadable into the generated its. For ease of integration the additional loadable is created as atf_(x+1) after all others to re-use core generation loops. Tested against the combinations of 1-part-atf and multi-part-atf each time with and without a tee binary present. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10ram: rk3328: Fix loading of skew valuesSimon South
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10ram: rk3328: Use correct frequency units in functionSimon South
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: dts: rk3328: rock64: Add same-as-spl orderEmmanuel Vadot
rk3328 can use same-as-spl option so next loaders are loaded from the same medium. Add the boot order in the rock64 dts otherwise booting from sdcard will result in u-boot looking into the eMMC. Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10rockchip: rk3399: Add Leez P710 supportAndy Yan
Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <andyshrk@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk809: support rk809 pmicJoseph Chen
The RK809 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk817: support rk817 pmicJoseph Chen
The RK817 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk805: support rk805 pmicElaine Zhang
The RK805 are a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 3*LDOs) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk816: support rk816 pmicElaine Zhang
The RK816 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: regulator: rk8xx: update the driver for rk808 and rk818Elaine Zhang
In order to adapt the following pmics, make the interface more compatible. Support buck and ldo suspend voltage setting and getting. Supprot buck and ldo suspend enable/disable setting and getting. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10dm: regulator: support regulator more stateJoseph Chen
support parse regulator standard property: regulator-off-in-suspend; regulator-init-microvolt; regulator-suspend-microvolt: regulator_get_suspend_enable regulator_set_suspend_enable regulator_get_suspend_value regulator_set_suspend_value Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-08Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- Assorted fixes
2019-11-08tools/img2brec.sh: Delete unused toolTom Rini
This script was only used on the MX1ADS board (and possibly other MX1 platforms) to program the flash. As we no longer have any boards for that SoC, remove this tool. Fixes: e570aca9474b ("mx1ads: remove board support") Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-08Merge branch '2019-11-07-master-imports'Tom Rini
- Add Phytium Durian Board - Assorted bugfixes - Allow for make ERR_PTR/PTR_ERR architecture specific
2019-11-08Merge branch '2019-11-07-ti-imports'Tom Rini
- LogicPD platform fixes - Adaptive Voltage Scaling (AVS) support - Minor bugfixes
2019-11-08cmd: move down CONFIG_CMD_BOOTEFI after CONFIG_BOOTM_VXWORKSAKASHI Takahiro
Due to the commit 4b0bcfa7c4ec ("Kconfig: Migrate CONFIG_BOOTM_* options") BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are displayed in a long distance. This will make it difficult for us to understand that those configurations are closely related. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-08freescale/powerpc: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08freescale/layerscape: Rename the config CONFIG_SECURE_BOOT nameUdit Agarwal
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08configs: spi: Add the SPI_FLASH_BAR for ESPIXiaowei Bao
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix warning if no hwconfig is definedPankaj Bansal
While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
2019-11-08usb: xhci: support 1.1 or later versionChunfeng Yun
The xHCI 1.1 version also need set Transfer Type field Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-08drivers: net: fsl_enetc: fix RGMII configurationMichael Walle
Add the missing RGMII PHY modes in which case the MAC has configure its RGMII settings. The only difference between these modes is the RX and TX delay configuration. A user might choose any RGMII mode in the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08drivers: net: fsl_enetc: set phydev->nodeMichael Walle
The saved ofnode is used by some PHY drivers to access the device tree node of the PHY. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-layerscape: introduce fsl_board_late_init()Michael Walle
The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_xMichael Walle
The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls1028a: add erratum A-050382 workaroundLaurentiu Tudor
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: lx2160a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: add missing SATA3 and SATA4 base addressesLaurentiu Tudor
LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: ls2088a: add icid setup for platform devicesLaurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: fsl-layerscape: guard caam specific definesLaurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08fsl-layerscape: do not use layerscape EFI reset if PSCI usedMathew McBride
If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08armv8: dts: ls1088a: add PSCI binding for LS1088AMathew McBride
This allows the use of PSCI calls to trusted firmware to initiate reset and poweroff events with CONFIG_PSCI_RESET and CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target board has implemented a custom reset or poweroff procedure in EL3. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08pci: layerscape: Only set EP CFG READY bitPankaj Bansal
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit of pci controller is set, so that RC can read the config space of EP. While setting the config ready bit, LTSSM_EN bit in same register was also inadvertently getting cleared. This restarts the link training between RC and EP. Update code to just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-07configs: j721e_evm_r5_defconfig: Remove SPL multi-DTB FIT supportAndrew F. Davis
The SPL FIT will only have one DTB, so remove support for multi-DTB. This also removes an early access to EEPROM used to select the DTB that is not valid in SPL at the point at which it is accessed, that always returns false for GP devices and causes a firewall expection on HS. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07Kconfig: ti: Make board detect EEPROM addresses depend BOARD_DETECTAdam Ford
There is an option to enable the board detection for TI platforms. If this is option is not set, there is no reason to set the EEPROM bus address or chip address. This patch makes both EEPROM_BUS_ADDRESS and EEPROM_CHIP_ADDRESS depend on TI_I2C_BOARD_DETECT. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07configs: omap3_logic_somlv: Remove GPIO from SPLAdam Ford
The SPL is too tight, and it cannot start any longer. To help reduce the size of SPL, we need to remove some non-critical features. This patch removes SPL_GPIO_SUPPORT to free up some operating space. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: dts: logicpd-som-lv-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07Revert "ARM: omap3_logic/omap35_logic: Enable GPIO in SPL"Adam Ford
The SPL is too tight, and it cannot start any longer. To help reduce the size of SPL, we need to remove some non-critical features. This reverts commit 66063a7c1388fb724e8671b03c529fb5cda992dd. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Remove unused GPIOAdam Ford
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight. This patch removes the all but GPIO4 from the spl device tree to reduce the SPL footprint. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07ARM: omap3_logic: Power on MMC when setting up PMICAdam Ford
The PMIC enables power to the MMC card by default, but depending on the state it was left when restarted, it's possible the MMC may be powered down. This patch patch explicitly tells the twl4030 to power the MMC. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07configs: j721e_evm_r5_defconfig: Enable AVS Class 0 & dependent configsKeerthy
Enable AVS Class 0 & dependent config options. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07configs: am65x_evm_r5_defconfig: Enable AVS class 0 supportTero Kristo
Enable AVS class 0 support for the R5 SPL bootloader. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07configs: am65x_evm_r5_defconfig: Enable TPS62363 regulator supportTero Kristo
TPS62363 is used to control the MPU_VDD voltage, so enable the driver for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supplyKeerthy
Hook buck12_reg to vtm avs supply Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 nodeKeerthy
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-j721e-r5-common-proc-board: Add VTM nodeKeerthy
Add VTM node for voltage and thermal management. For u-boot, this is needed for supporting AVS class 0, as the efuse values for the OPPs are stored under the VTM. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: enable wkup_vtm0 node and link in suppliesTero Kristo
Link the vdd-supplies for the voltage domains under the VTM node. Also, enable the node under SPL. This will enable the AVS class 0 support on am65x-evm board. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07arm: dts: k3-am654-r5-base-board: add supply rail for MPUTero Kristo
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached to i2c0 bus. Add device node for this so that it can be controlled via a regulator driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
generated by cgit (git 2.34.1) at 2025-01-09 01:52:01 +0000