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path: root/arch/riscv/Kconfig
AgeCommit message (Expand)Author
2019-06-05riscv: Add Microchip MPFS Icicle board supportPadmarao Begari
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner
2019-05-18CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: implement IPI platform functions using SBILukas Auer
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-11-26riscv: add Kconfig entries for the C and A ISA extensionsLukas Auer
2018-11-26riscv: select CONFIG_PHYS_64BIT on RV64I systemsLukas Auer
2018-11-26riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer
2018-10-03riscv: Add QEMU virt board supportBin Meng
2018-10-03riscv: kconfig: Normalize architecture name spellingBin Meng
2018-05-29riscv: cpu: nx25: Rename as ax25Rick Chen
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen