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path: root/arch/x86/include
AgeCommit message (Expand)Author
2015-01-24x86: Implement a cache for Memory Reference Code parametersSimon Glass
2015-01-24x86: Use ipchecksum from net/Simon Glass
2015-01-23x86: Test mtrr support flag before accessing mtrr msrBin Meng
2015-01-23x86: Save mtrr support flag in global dataBin Meng
2015-01-23x86: Support ROMs on other archsSimon Glass
2015-01-13x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass
2015-01-13x86: Add support for MTRRsSimon Glass
2015-01-13x86: Drop RAMTOP KconfigSimon Glass
2015-01-12x86: Simplify the fsp hob access functionsBin Meng
2015-01-12pci: Make pci apis usable before relocationBin Meng
2014-12-18x86: Clean up the FSP support codesBin Meng
2014-12-18x86: crownbay: Add SPI flash supportBin Meng
2014-12-18x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng
2014-12-18x86: Add basic support to queensbay platform and crownbay boardBin Meng
2014-12-15x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada
2014-12-13x86: Support Intel FSP initialization path in start.SBin Meng
2014-12-13x86: Add post failure codes for bist and carBin Meng
2014-12-13x86: queensbay: Adapt FSP support codesBin Meng
2014-12-13x86: Initial import from Intel FSP release for Queensbay platformBin Meng
2014-12-13x86: Add a simple superio driver for SMSC LPC47MBin Meng
2014-12-13x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng
2014-12-08Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada
2014-11-25x86: Add initial video device init for Intel GMASimon Glass
2014-11-25x86: Add GDT descriptors for option ROMsSimon Glass
2014-11-25x86: ivybridge: Add northbridge init functionsSimon Glass
2014-11-25x86: Drop some msr functions that we don't supportSimon Glass
2014-11-25x86: Add init for model 206AX CPUSimon Glass
2014-11-25x86: Add LAPIC setup codeSimon Glass
2014-11-25x86: Refactor interrupt_init()Bin Meng
2014-11-25x86: Remove cpu_init_r() for x86Bin Meng
2014-11-25x86: Add Intel speedstep and turbo mode codeSimon Glass
2014-11-25x86: ivybridge: Set up XHCI USBSimon Glass
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass
2014-11-25x86: ivybridge: Add SATA initSimon Glass
2014-11-25x86: ivybridge: Add PCH initSimon Glass
2014-11-25x86: Add a simple header file for ACPISimon Glass
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass
2014-11-25x86: Set up edge triggering on interrupt 9Simon Glass
2014-11-25x86: pci: Add handlers before and after a PCI hose scanSimon Glass
2014-11-25x86: Add ioapic.h headerSimon Glass
2014-11-21x86: ivybridge: Implement SDRAM initSimon Glass
2014-11-21x86: ivybridge: Add LAPIC supportSimon Glass
2014-11-21x86: ivybridge: Add support for early GPIO initSimon Glass
2014-11-21x86: ivybridge: Add early init for PCH devicesSimon Glass
2014-11-21x86: ivybridge: Perform Intel microcode update on bootSimon Glass
2014-11-21x86: ivybridge: Perform initial CPU setupSimon Glass
2014-11-21x86: Add msr read/write functions that use a structureSimon Glass
2014-11-21x86: Add clr/setbits functionsSimon Glass
2014-11-21x86: ivybridge: Add early LPC init so that serial worksSimon Glass
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