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2018-04-26ARM: rmobile: Update M2-N GoseMarek Vasut
The M2-N Gose port was broken since some time. This patch updates the M2-N Gose port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26ARM: rmobile: Update H2 LagerMarek Vasut
The H2 Lager port was broken since some time. This patch updates the H2 Lager port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26imx6ul: opos6ul: in Serial Downloader boot mode use ymodemSébastien Szymanski
When booting in Serial Downloader mode load the U-Boot image using ymodem. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26imx6ul: opos6ul: add SPL_DM supportSébastien Szymanski
Since commit commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support makes the board boot again. Fixes: commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26arm,imx6: fix PAD_CTL_SPEED_LOW constantMark Jonas
For most i.MX6 processors the PAD_CTL_SPEED_LOW constant is the same. Only the i.MX6 SoloLite is an exemption. So far the code did not consider that. Additionally, for a few i.MX6 processors the code used the wrong value for the constant. This patch fixes the PAD_CTL_SPEED_LOW constant for: - i.MX6 Solo [1] - i.MX6 DualLite [1] - i.MX6 Dual [2] - i.MX6 Quad [2] - i.MX6 DualPlus [3] - i.MX6 QuadPlus [3] Before, it was already correct for: - i.MX6 SoloLite [4] - i.MX6 SoloX [5] - i.MX6 UtraLite [6] - i.MX6 ULL [7] [1] https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf [2] https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf [3] https://www.nxp.com/docs/en/reference-manual/iMX6DQPRM.pdf [4] https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf [5] https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf [6] https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf [7] https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-04-25rockchip: enable SYS_NS16550 for all SoCs by defaultKever Yang
All rockchip SoCs can use ns16550 driver, enable it for all and set SYS_NS16550_MEM32 for all SoCs. Version-changes: 2 - use imply instead of select Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: rk322x: update MACRO for back-to-bromKever Yang
The MACRO has been update after: ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL We need to update the C code for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25arm: rockchip: make_fit_atf: remove unneeded importsPatrick Uiterwijk
These imports are entirely unused in the entire script. Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org> Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: rk3188: use DM timer instead of rk_timerKever Yang
Disable rk_timer as SYS timer and use DM timer instead, so that we can get a better timer framework, the rk_timer is going to be clean after we conver to use DM timer or ARM arch/generic timer. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: rk3188: add timer3 nodeKever Yang
Add dts node for timer3. Because of the rockchip timer can only KNOWN "dtd_rockchip_rk3368_timer" with OF_PLATDATA enable, so we override its compatible to "rockchip,rk3368-timer". Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: rk3188: add -u-boot.dtsi for rock-rk3188Kever Yang
We should a -u-boot.dtsi for those config need by U-Boot only, and other part sync with kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-23Merge git://git.denx.de/u-boot-uniphierTom Rini
2018-04-24ARM: dts: uniphier: drop u-boot, dm-pre-reloc from SD/eMMC clock nodeMasahiro Yamada
Now that the SD/eMMC driver does not use the clock driver in SPL, remove u-boot,dm-pre-reloc properties to let the fdtgrep tool drop the unnecessary nodes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-23arm: zynq: Enable setup board name for different boardsMichal Simek
There is no need to use zynq name as SYS_BOARD for all boards. The patch is adding an option to change it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23nand: zynq: Cleanup initializationEzequiel Garcia
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the driver doesn't have to play any ifdef game. Also, we can mark zynq_nand_init() as static and get rid of the mach-specific nand.h header. This is really a revert of: "mtd: zynq: nand: Move board_nand_init() function to board.c" (sha1: 310995d9f91ae56082b49be06fe8c3d01424f8f6) Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-21ARM: rmobile: Update E2 SilkMarek Vasut
The E2 Silk port was broken since some time. This patch updates the E2 Silk port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- NOTE: The port is missing support for I2C1 for DA9063 reset, since the I2C driver needs to be converted to DM and DT probing. That's not an issue for this patch though, since the reset was broken on Silk since forever.
2018-04-18Merge git://git.denx.de/u-boot-uniphierTom Rini
2018-04-18Merge git://git.denx.de/u-boot-shTom Rini
2018-04-18ARM: dts: uniphier: sync DT with Linux 4.17-rc1Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-17Merge git://git.denx.de/u-boot-socfpgaTom Rini
2018-04-17ARM: rmobile: Update M2 KoelschMarek Vasut
The M2 Koelsch port was broken since some time. This patch updates the M2 Koelsch port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17ARC: Remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.cEugeniy Paltsev
"Global data" structure "gd" is not used in init_helpers.c thus DECLARE_GLOBAL_DATA_PTR might be safely removed. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17arm: dts: socfpga: add reset propertyDinh Nguyen
Add reset dts property to the i2c nodes. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17arm: dts: socfpga: enables i2c0 in socfpga_de0_nanoDinh Nguyen
Add all the appropriate i2c alias in the base socfpga dtsi and enables the i2c node on the DE0 NANO board. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17ARM: dts: stratix10: Add base dtsi and devkit dtsDinh Nguyen
From the Linux v4.16-rc4, add the base dtsi and devkit dts files for the Stratix10 SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17arm: socfpga: stratix10: Add base address map for Statix10 SoCChin Liang See
Add the base address map for Stratix10 SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17ARM: rmobile: Enable RPC QSPI on R8A77970 V3M EagleMarek Vasut
Enable the RPC QSPI driver on R8A77970 V3M Eagle and configure the environment layout to match that used by old U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17ARM: rmobile: Add Renesas RPC HF/QSPI DT nodesMarek Vasut
Add device tree nodes for the Renesas RPC HF/QSPI controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-16bios: vesa: Guard setting vesa mode with CONFIG_FRAMEBUFFER_SET_VESA_MODEBin Meng
If CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set, don't switch graphics card to VESA mode. This applies to both native mode and emulator mode of running the VGA BIOS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16x86: Rename e820entry to e820_entryBin Meng
This changes 'struct e820entry' to 'struct e820_entry' to conform with the coding style. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16x86: Use 'unsigned int' in install_e820_map() functionsBin Meng
This fixes the following checkpatch warning: warning: Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16x86: Update the io.h file to use {out|in}_{be|le}X macrosLukasz Majewski
The commit 3f70a6f57734 ("x86: Add clr/setbits functions") introduced the {read|write}_ macros to manipulate data. Those macros are not used by any code in the u-boot project (despite the io.h itself). Other architectures use io.h with {in|out}_* macros. This commit brings some unification across u-boot supported architectures. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-16x86: Add 64-bit memory-mapped I/O functionsIvan Gorinov
Add readq() and writeq() definitions for x86. Please note: in 32-bit code readq/writeq will generate two 32-bit memory access instructions instead of one atomic 64-bit operation. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-15Merge git://git.denx.de/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15imx: Create distinct pre-processed mkimage config filesTrent Piepho
Each imx image is created by a separate sub-make and during this process the mkimage config file is run though cpp. The cpp output is to the same file no matter what imx image is being created. This means if two imx images are generated in parallel they will attempt to independently produce the same pre-processed mkimage config file at the same time. Avoid the problem by making the pre-processed config file name unique based on the imx image it will be used in. This way each image will create a unique config file and they won't clobber each other when run in parallel. This should fixed the build bug referenced in b5b0e4e3 ("imximage: Remove failure when no IVT offset is found"). Cc: Breno Lima <breno.lima@nxp.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15mx31ads: DeleteTom Rini
This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15imx31_phycore: DeleteTom Rini
This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15imx: mx7: snvs: Add an SNVS init routineBryan O'Donoghue
Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-04-15imx: board: Add support for the K+P's kp_imx6q_tpc boardLukasz Majewski
This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds
2018-04-15imx: hab: Provide hab_auth_img_or_fail commandBryan O'Donoghue
This patch adds hab_auth_img_or_fail() a command line function that encapsulates a common usage of authenticate and failover, namely if authenticate image fails, then drop to BootROM USB recovery mode. For secure-boot systems, this type of locked down behavior is important to ensure no unsigned images can be run. It's possible to script this logic but, when done over and over again the environment starts get very complex and repetitive, reducing that script repetition down to a command line function makes sense. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Breno Lima <breno.lima@nxp.com>
2018-04-15imx: mx7: Add comment to describe OTP TESTER registersBryan O'Donoghue
The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15imx: mx7: Fix CONFIG_SERIAL_TAG compilationBryan O'Donoghue
Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to define "struct tag_serialnr". This structure is defined in <asm/setup.h>, this patch includes <asm/setup.h> to fix. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15ARM: mx6: ddr: Add write leveling correction codeMarek Vasut
When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this means is that the HW write leveling detected that the DQS rising edge on one or more bundles arrives slightly _after_ CLK and therefore when the DDR DRAM samples CLK on the DQS rising edge, the CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18). The HW write leveling then ends up adding almost an entire cycle (thus the 0x17f) to the DQS delay, which indeed aligns it, but also triggers subsequent calibration failure in DQS gating due to this massive offset. There are two observations here: - If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the DQS gating passes, the entire calibration passes as well and the DRAM is perfectly stable even under massive load. - When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so in MPWLDECTRx register is not there, but it is replaced by 0x0 as one would expect. Someone from NXP finally explains why, quoting [1]: " Having said all that, the DDR Stress Test does something that we do not advertise to the users. The Stress Test iself looks at the values of the MPWLDECTRL0/1 fields before reporting results, and if it sees any filed with a value greater than 200/256 delay (reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR Stress test will reset the Write Leveling delay for this lane to 0x000 and not report it in the log. The reason that the DDR Stress test does this is because a delay of more than 78% a clock cycle means that the DQS edge is arriving within the JEDEC tolerence of 25% of the clock edge. In most cases, DQS is arriving < 5% tCK of the SDCLK edge in the early case, and it does not make sense to delay the DQS strobe almost a full clock cycle and add extra latency to each Write burst just to make the two edges align exactly. In this case, we are guilty of making a decision for the customer without telling them we are doing it so that we don't have to provide the above explanation to every customer. They don't need to know it. " This patch adds the correction described above, that is if the MPWLDECTRx value is over 0x148, the value is corrected back to 0x0. [1] https://community.nxp.com/thread/456246 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-04-13ARM: rmobile: Convert TPL to SPLMarek Vasut
There is currently no use for building the SPL anymore, since the SPI loader can easily be replaced by TPL and TPL does load U-Boot directly. Upgrade TPL to SPL and replace what used to be SPL with it. This way we build the U-Boot sources only twice, not thrice. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13ARM: rmobile: Shrink the TPLMarek Vasut
Shrink the TPL by using tiny printf and tiny memset by default. This removes the biggest symbol -- vsnprintf_internal -- from the TPL and reduces the text segment by about 2 kiB. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13ARM: rmobile: Update H2 StoutMarek Vasut
The H2 Stout port was broken since some time. This patch updates the H2 Stout port to use modern frameworks, DM, DT probing, SPL and TPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13ARM: rmobile: Enable SCIFA0 early on H2 StoutMarek Vasut
The H2 Stout uses SCIFA0 for serial console, make sure it is available very early on when probing from DT. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13vxworks: fixed cpu enable using PSCI on armv8Vasyl Vavrychuk
Without armv8_setup_psci register VBAR_EL3 is not set up property which makes SMC calls jump to invalid location. smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt. Without this they will never pursue booting process. Fix was applied to the two ways of booting VxWorks: bootvx and bootm commands. This implementation is very similar to what is done in boot_jump_linux in arch/arm/lib/bootm.c file. Tested on VxWorks 7 release SR0520 2017-12-08 Intel Stratix 10 SX SoC Development Kit board. Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@globallogic.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-11ARM: rmobile: Fix the memory map on Gen3Marek Vasut
Fix up the memory map on Gen3 to match datasheet properly. This simplifies the memory map setup as well, since we do no longer need this massive complexity. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11ARM: rmobile: Add JTAG recovery support for M2 PorterMarek Vasut
Add JTAG recovery support into the M2 Porter TPL. This allows the TPL to be loaded over JTAG, initialize the system, wait for the JTAG debugger to load U-Boot image into RAM and then resume and start U-Boot from RAM. The procedure is as follows: 1) Load u-boot-tpl.bin to 0xe6300000 2) Write magic number 0x1337c0de to 0xe6300020 TPL checks for this particular magic and starts JTAG recovery if this number is present. This is not present by default. 3) Start U-Boot TPL from 0xe6300000 4) Wait for a message from TPL on UART indicating JTAG boot: "JTAG boot detected!" 5) Halt the system in JTAG debugger 6) Load U-Boot image (u-boot.img) to 0x4fffffc0 7) Write magic number 0xb33fc0de to 0xe6300024 TPL checks for this particular magic to verify that the U-Boot image was loaded into DRAM by the JTAG debugger. 8) Resume the system in JTAG debugger Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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