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path: root/drivers/spi
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2020-02-04spi: ich: Drop while loop in hardware sequencing erase caseWolfgang Wallner
When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. See http://patchwork.ozlabs.org/patch/1222779/ for more detailed background information and discussion. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-27spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra
Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra
Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add direct mode supportVignesh Raghavendra
Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra
Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra
Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: prevent overriding established bus settingsMarcin Wojtas
The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27dm: spi: Check cs number before accessing slavesBin Meng
Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle
This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-23spi: bcm63xx-hsspi: allow to use this driver on arm bcm68360Philippe Reynes
This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-17common: Move clock functions into a new fileSimon Glass
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-14spi: Fix manual relocation calling more timesAshok Reddy Soma
When two instances of AXI QSPI with flash are added and tested simultaneously the spi driver operations are relocated twice. As a result code is accessing addresses outside of RAM when relocated second time which is causing a crash. Tested on Microblaze. Similar change was done in past by: commit f238b3f0fbc9 ("watchdog: dm: Support manual relocation for watchdogs") commit 2588f2ddfd60 ("dm: sf: Add support for all targets which requires MANUAL_RELOC") commit 1b4c2aa25bdf ("gpio: dm: Support manual relocation for gpio") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-06Merge branch 'next'Tom Rini
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
2019-12-27spi: rk: Limit transfers to (64K - 1) bytesJagan Teki
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-15spi: ich: Add Apollo Lake supportSimon Glass
Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Add TPL supportSimon Glass
In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Add support for get_mmap() methodSimon Glass
Add this method so that the memory-mapped location of the SPI flash can be queried. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Support hardware sequencingSimon Glass
Apollo Lake (APL) only supports hardware sequencing. Add support for this into the SPI driver, as an option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Support of-platdata for fast-spiSimon Glass
The Intel Fast SPI interface is similar to ICH. Add of-platdata support for this using the "intel,fast-spi" compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Correct max-size bug in ich_spi_adjust_size()Simon Glass
This incorrectly shortens read operations if there is a maximum write size but no maximum read size. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Add mmio_base to struct ich_spi_platdataSimon Glass
It is useful to store the mmio base in platdata. It reduces the amount of casting needed. Update the code and move the struct to the C file at the same time, as we will need to use with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Various small tidy-upsSimon Glass
Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Fix header orderSimon Glass
Move the header files into the right order. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Convert to livetreeSimon Glass
Use dev_get_driver_data() to obtain the device type. It has the same effect and is shorter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Move the protection/lockdown code into a functionSimon Glass
Reduce the size of the probe function but putting this code into its own function. Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: ich: Move init function just above probe()Simon Glass
It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: spi: Don't enable SPI_FLASH_BAR by defaultSimon Glass
We don't normally need this on x86 unless the size of SPI flash devices is larger than 16MB. This can be enabled by particular SoCs as needed, since it adds to code size. Drop the default enabling of this option on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15spi: Correct operations check in dm_spi_xfer()Simon Glass
At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15dm: gpio: Allow control of GPIO uclass in SPLSimon Glass
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move get_ticks() function out of common.hSimon Glass
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-20spi: cadence_qspi: support DM_CLKSimon Goldschmidt
Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-08configs: spi: Add the SPI_FLASH_BAR for ESPIXiaowei Bao
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-03spi: Add support for memory-mapped flashSimon Glass
On x86 platforms the SPI flash can be mapped into memory so that the contents can be read with normal memory accesses. Add a new SPI method to find the location of the SPI flash in memory. This differs from the existing device-tree "memory-map" mechanism in that the location can be discovered at run-time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
2019-10-25Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-25spi: mt7621-spi: restore default register value after each xferWeijie Gao
Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao
The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: use clock frequency from clk driverWeijie Gao
This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: designware_spi: Disable and free clock when remove driverLey Foon Tan
Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi: Kconfig: Enable SPI_SUNXI for SUNXIJagan Teki
SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25dm: spi: Change cs_info op to return -EINVAL for invalid cs numBin Meng
We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25dm: spi: Return 0 if driver does not implement ops->cs_infoBin Meng
If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi: Kconfig: Add help textJagan Teki
Add detailed help text for SPI support. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi: zynqmp: Remove unused platform headersMichal Simek
There is no reason to include clk.h and hardware.h headers. Driver doesn't require them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-15dm: spi: Do not assume first SPI busThomas Fitzsimmons
When CONFIG_OF_PRIOR_STAGE is enabled, this workaround was needed before device_bind_common assigned request numbers sequentially in the absence of aliases. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
2019-10-11spi: bcm63xx_hsspi: Continue init when using no reset and fixed-clock.Kursad Oney
The Broadcom ARM implementations do not yet have a clock framework so one can use a fixed clock as the root clock of the hsspi block. The fixed clock does not have an "enable" routine, since it's always enabled. So when we hit this issue, getting an ENOSYS return, do not bail but continue initialization. Similarly the block might already have been out of reset, say, when we are booting from a SPI device. So if the reset signal is not configured in the device tree, do not bail out and instead skip deasserting the reset. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11spi: bcm63xx_hsspi: switch to raw I/O functions.Kursad Oney
Make the driver compatible with both big and little endian SOCs. Replace big-endian calls with their raw equivalents, expect for writing the command to FIFO. That still has to be in big-endian format. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-11spi: hsspi: allow to be used on bcm6858 and bcm63158Kursad Oney
This IP exists in both MIPS and ARM cores, so we also allow to use this driver on bcm6858 and bcm63158. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-27 02:15:48 +0000