Merge branch 'master' of git://git.denx.de/u-boot-arm

author: Stefano Babic <sbabic@denx.de> 2014-08-08 10:18:40 +0200
committer: Stefano Babic <sbabic@denx.de> 2014-08-08 10:18:40 +0200
commit: c23154aab5825fec81d5500c53eaa686646c76b5 (patch)
tree: 32b0aafae49f664a65ced50981492bb031f006b8
parent: cb07d74e2e0c0a41533b6bcd551af9bf2ebcf2bc (diff)
parent: 9d195a546179bc732aba9eacccf0a9a3db591288 (diff)
290 files changed, 8923 insertions, 3147 deletions
diff --git a/.gitignore b/.gitignore
index 2ddf57f2a5..0ace33bd61 100644
--- a/.gitignore
+++ b/.gitignore
@@ -44,11 +44,7 @@
 #
 # Generated files
 #
-
 /LOG
-/errlog
-/reloc_off
-
 /spl/
 /tpl/
 
diff --git a/.mailmap b/.mailmap
new file mode 100644
index 0000000000..e1c666334a
--- /dev/null
+++ b/.mailmap
@@ -0,0 +1,27 @@
+#
+# This list is used by git-shortlog to fix a few botched name translations
+# in the git archive, either because the author's full name was messed up
+# and/or not always written the same way, making contributions from the
+# same person appearing not to be so or badly displayed.
+#
+# This file can be modified by hand or updated by the following command:
+#  scripts/mailmapper > tmp; mv tmp .mailmap
+#
+
+Allen Martin <amartin@nvidia.com>
+Andreas Bießmann <andreas.devel@googlemail.com>
+Aneesh V <aneesh@ti.com>
+Dirk Behme <dirk.behme@googlemail.com>
+Fabio Estevam <fabio.estevam@freescale.com>
+Jagannadha Sutradharudu Teki <402jagan@gmail.com>
+Markus Klotzbuecher <mk@denx.de>
+Prabhakar Kushwaha <prabhakar@freescale.com>
+Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Sandeep Paulraj <s-paulraj@ti.com>
+Shaohui Xie <Shaohui.Xie@freescale.com>
+Stefan Roese <stroese>
+Stefano Babic <sbabic@denx.de>
+TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Wolfgang Denk <wdenk>
+York Sun <yorksun@freescale.com>
+Łukasz Majewski <l.majewski@samsung.com>
diff --git a/Makefile b/Makefile
index 5277781bb8..80eb239d93 100644
--- a/Makefile
+++ b/Makefile
@@ -915,6 +915,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
 u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
 	$(call if_changed,pad_cat)
 
+MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
+u-boot-nand.gph: u-boot.bin FORCE
+	$(call if_changed,mkimage)
+	@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+
 ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
@@ -1137,7 +1143,7 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 tpl/u-boot-tpl.bin: tools prepare
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
 
-TAG_SUBDIRS := $(u-boot-dirs) include
+TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
 
 FIND := find
 FINDFLAGS := -L
@@ -1147,7 +1153,7 @@ tags ctags:
 						-name '*.[chS]' -print`
 
 etags:
-		etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
+		etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
 						-name '*.[chS]' -print`
 cscope:
 		$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
@@ -1222,7 +1228,7 @@ CLOBBER_FILES += u-boot* MLO* SPL System.map
 MRPROPER_DIRS  += include/config include/generated          \
 		  .tmp_objdiff
 MRPROPER_FILES += .config .config.old \
-		  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
+		  ctags etags cscope* GPATH GTAGS GRTAGS GSYMS \
 		  include/config.h include/config.mk
 
 # clean - Delete most, but leave enough to build external modules
@@ -1311,7 +1317,8 @@ help:
 	@echo  '  dir/file.[oisS] - Build specified target only'
 	@echo  '  dir/file.lst    - Build specified mixed source/assembly target only'
 	@echo  '                    (requires a recent binutils and recent build (System.map))'
-	@echo  '  tags/TAGS	  - Generate tags file for editors'
+	@echo  '  tags/ctags	  - Generate ctags file for editors'
+	@echo  '  etags		  - Generate etags file for editors'
 	@echo  '  cscope	  - Generate cscope index'
 	@echo  '  ubootrelease	  - Output the release version string'
 	@echo  '  ubootversion	  - Output the version stored in Makefile'
diff --git a/README b/README
index 37e4d1b09d..cdccae9953 100644
--- a/README
+++ b/README
@@ -3751,6 +3751,22 @@ Configuration Settings:
 - CONFIG_SYS_MALLOC_LEN:
 		Size of DRAM reserved for malloc() use.
 
+- CONFIG_SYS_MALLOC_F_LEN
+		Size of the malloc() pool for use before relocation. If
+		this is defined, then a very simple malloc() implementation
+		will become available before relocation. The address is just
+		below the global data, and the stack is moved down to make
+		space.
+
+		This feature allocates regions with increasing addresses
+		within the region. calloc() is supported, but realloc()
+		is not available. free() is supported but does nothing.
+		The memory will be freed (or in fact just forgotton) when
+		U-Boot relocates itself.
+
+		Pre-relocation malloc() is only supported on sandbox
+		at present but is fairly easy to enable for other archs.
+
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 5fa182536d..c3b8289dcf 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -113,7 +113,7 @@ endif
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
-OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif
 
 ifdef CONFIG_OF_EMBED
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 232118d7f4..703ce8c640 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -21,6 +21,11 @@ endif
 ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
 obj-y	+= nonsec_virt.o
 obj-y	+= virt-v7.o
+obj-y	+= virt-dt.o
+endif
+
+ifneq ($(CONFIG_ARMV7_PSCI),)
+obj-y	+= psci.o
 endif
 
 obj-$(CONFIG_KONA) += kona-common/
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index c4af252110..f8519c0403 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -8,9 +8,12 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
-obj-y	+= keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y	+= msmc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-y	+= ddr3.o
+obj-y	+= keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644
index 0000000000..42092e1060
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case DDR3_PLL:
+			ret = external_clk[ddr3_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:      return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
new file mode 100644
index 0000000000..96a9f72886
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = KS2_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:	return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
+	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
+	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6..03c1d9f660 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -8,9 +8,6 @@
  */
 
 #include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
@@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
 	}
 }
 
-struct pll_regs {
-	u32	reg0, reg1;
-};
-
-static const struct pll_regs pll_regs[] = {
-	[CORE_PLL]	= { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
-	[PASS_PLL]	= { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
-	[TETRIS_PLL]	= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
-	[DDR3A_PLL]	= { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
-	[DDR3B_PLL]	= { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
-};
-
-/* Fout = Fref * NF(mult) / NR(prediv) / OD */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(K2HK_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				 PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = K2HK_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = K2HK_ARMPLLCTL0;
-			break;
-		case DDR3A_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = K2HK_DDR3APLLCTL0;
-			break;
-		case DDR3B_PLL:
-			ret = external_clk[ddr3b_clk];
-			reg = K2HK_DDR3BPLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:	return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
-	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
-	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-	return 0;
-}
-
 void init_pll(const struct pll_init_data *data)
 {
 	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
 		tmp = pllctl_reg_read(data->pll, secctl);
 
 		if (tmp & (PLLCTL_BYPASS)) {
-			setbits_le32(pll_regs[data->pll].reg1,
+			setbits_le32(keystone_pll_regs[data->pll].reg1,
 				     BIT(MAIN_ENSAT_OFFSET));
 
 			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
 
 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
 
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
-				(pllm << 6));
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLLM_MULT_HI_SMASK, (pllm << 6));
 
 		/* Set the BWADJ     (12 bit field)  */
 		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_BWADJ_LO_SMASK,
 				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
-		clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+				PLL_BWADJ_HI_MASK,
 				(tmp_ctl >> 8));
 
 		/*
 		 * Set the pll divider (6 bit field) *
 		 * PLLD[5:0] is located in MAINPLLCTL0
 		 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_DIV_MASK, plld);
 
 		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
 		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
 
 		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 
+#ifndef CONFIG_SOC_K2E
 	} else if (data->pll == TETRIS_PLL) {
 		bwadj = pllm >> 1;
 		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
-		setbits_le32(pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
+		setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
 		/*
 		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
-		setbits_le32(pll_regs[data->pll].reg1 ,
+		setbits_le32(keystone_pll_regs[data->pll].reg1 ,
 			     PLL_PLLRST | PLLCTL_ENSAT);
 
 		/*
@@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << 6) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 		/*
 		 * 5 Wait for at least 5 us based on the reference
 		 * clock (PLL reset time)
@@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 
 		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
-		clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
 		/*
 		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
 		 * (PLL lock time)
 		 */
 		sdelay(105000);
 		/* 8 disable bypass */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		/*
 		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
 	} else {
-		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 		/*
 		 * process keeps state of Bypass bit while programming
 		 * all other DDR PLL settings
 		 */
-		tmp = __raw_readl(pll_regs[data->pll].reg0);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
 		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
 
 		/*
@@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << PLL_MULT_SHIFT) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT);
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
@@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
 		if (data->pll == PASS_PLL)
 			tmp |= PLLCTL_PAPLL;
 
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
 		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
 		tmp = PLL_PLLRST;
 		/* Set RESET bit = 1 */
-		setbits_le32(pll_regs[data->pll].reg1, tmp);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		/* Wait for a minimum of 7 us*/
 		sdelay(21000);
 		/* Clear RESET bit */
-		clrbits_le32(pll_regs[data->pll].reg1, tmp);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		sdelay(105000);
 
 		/* clear BYPASS (Enable PLL Mode) */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 	}
 
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index afd30f3853..d97c95be11 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -14,10 +14,10 @@
 #include <asm/arch/psc_defs.h>
 
 struct pll_init_data cmd_pll_data = {
-	.pll			= MAIN_PLL,
-	.pll_m			= 16,
-	.pll_d			= 1,
-	.pll_od			= 2,
+	.pll = MAIN_PLL,
+	.pll_m = 16,
+	.pll_d = 1,
+	.pll_od = 2,
 };
 
 int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (strncmp(argv[1], "pa", 2) == 0)
 		cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
 	else if (strncmp(argv[1], "arm", 3) == 0)
 		cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
 	else if (strncmp(argv[1], "ddr3a", 5) == 0)
 		cmd_pll_data.pll = DDR3A_PLL;
 	else if (strncmp(argv[1], "ddr3b", 5) == 0)
 		cmd_pll_data.pll = DDR3B_PLL;
+#else
+	else if (strncmp(argv[1], "ddr3", 4) == 0)
+		cmd_pll_data.pll = DDR3_PLL;
+#endif
 	else
 		goto pll_cmd_usage;
 
@@ -51,11 +58,20 @@ pll_cmd_usage:
 	return cmd_usage(cmdtp);
 }
 
+#ifdef CONFIG_SOC_K2HK
 U_BOOT_CMD(
 	pllset,	5,	0,	do_pll_cmd,
 	"set pll multiplier and pre divider",
 	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
 );
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+	pllset, 5,      0,      do_pll_cmd,
+	"set pll multiplier and pre divider",
+	"<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -79,7 +95,12 @@ U_BOOT_CMD(
 	getclk,	2,	0,	do_getclk_cmd,
 	"get clock rate",
 	"<clk index>\n"
-	"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+	"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+	"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db76a3..2391e794e8 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,11 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <common.h>
+#include <asm/arch/ddr3.h>
 
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
 	unsigned int tmp;
 
@@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 		;
 }
 
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 {
 	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
 	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
+
+void ddr3_reset_ddrphy(void)
+{
+	u32 tmp;
+
+	/* Assert DDR3A  PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+	writel(tmp, KS2_DDR3APLLCTL1);
+
+	/* wait 10us to catch the reset */
+	udelay(10);
+
+	/* Release DDR3A PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+	__raw_writel(tmp, KS2_DDR3APLLCTL1);
+}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae..a8f8aee8ab 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,13 +10,14 @@
 #include <common.h>
 #include <ns16550.h>
 #include <asm/io.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 
 void chip_configuration_unlock(void)
 {
-	__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
-	__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
 int arch_cpu_init(void)
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
 	chip_configuration_unlock();
 	icache_enable();
 
-#ifdef CONFIG_SOC_K2HK
-	share_all_segments(8);
-	share_all_segments(9);
-	share_all_segments(10); /* QM PDSP */
-	share_all_segments(11); /* PCIE */
+	msmc_share_all_segments(8);  /* TETRIS */
+	msmc_share_all_segments(9);  /* NETCP */
+	msmc_share_all_segments(10); /* QM PDSP */
+	msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+	msmc_share_all_segments(13); /* PCIE 1 */
 #endif
 
 	/*
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 0000000000..11a9357db4
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,87 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/hardware.h>
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+	u32 i;
+
+	if (!(readl(KS2_DEVSTAT) & 0x1))
+		for (i = 0; i < length; i++, ptr++)
+			*ptr = cpu_to_be32(*ptr);
+
+	return 0;
+}
+
+static int turn_off_myself(void)
+{
+	printf("Turning off ourselves\r\n");
+	mon_power_off(0);
+
+	psc_disable_module(KS2_LPSC_TETRIS);
+	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+	asm volatile ("isb\n"
+		      "dsb\n"
+		      "wfi\n");
+
+	printf("What! Should not see that\n");
+	return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+	int i;
+
+	for (i = 0; i < num_dsps; i++) {
+		if (psc_disable_module(i + KS2_LPSC_GEM_0))
+			printf("Cannot disable module for #%d DSP", i);
+
+		if (psc_disable_domain(i + 8))
+			printf("Cannot disable domain for #%d DSP", i);
+	}
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return turn_off_myself();
+}
+
+U_BOOT_CMD(
+	killme, 1,      0,      do_killme_cmd,
+	"turn off main ARM core",
+	"turn off main ARM core. Should not live after that :(\n"
+);
+
+int misc_init_r(void)
+{
+	char *env;
+	long ks2_debug = 0;
+
+	env = getenv("ks2_debug");
+
+	if (env)
+		ks2_debug = simple_strtol(env, NULL, 0);
+
+	if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
+		turn_off_all_dsps(KS2_NUM_DSPS);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d20..7d8e5978df 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
 
 struct mpax {
 	u32	mpaxl;
@@ -56,9 +56,9 @@ struct msms_regs {
 };
 
 
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
 {
-	struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
 	int j;
 
 	for (j = 0; j < 8; j++) {
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc84d5..fa5422f2e8 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
 #define DEVICE_REG32_R(addr)			__raw_readl((u32 *)(addr))
 #define DEVICE_REG32_W(addr, val)		__raw_writel(val, (u32 *)(addr))
 
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE				K2HK_PSC_BASE
-#endif
-
 int psc_delay(void)
 {
 	udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
 	retry = 0;
 
 	do {
-		ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+		ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
 		ptstat = ptstat & (1 << domain_num);
 	} while ((ptstat != 0) && ((retry += psc_delay()) <
 		 PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
 	u32 domain_num;
 
 	/* Get the power domain associated with the module number */
-	domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+	domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
 				    PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
 
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * Get the power domain associated with the module number, and reset
 	 * isolation functionality
 	 */
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(v);
 	reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
 
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * change is made if the new state is power down.
 	 */
 	if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-		pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+		pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
 				       PSC_REG_PDCTL(domain_num));
 		pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
 					       PSC_REG_VAL_PDCTL_NEXT_ON);
-		DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+		DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
 			       pdctl);
 	}
 
 	/* Set the next state for the module to enabled/disabled */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	/* Trigger the enable */
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1<<domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	/* Wait on the complete */
 	return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
 		return 0;
 
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == 0)
 		return 0;
 	mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the reset isolation bit */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
 		return 0;
 
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
 	u32 pdctl;
 	u32 ptcmd;
 
-	pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+	pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
 	pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
 	pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
 
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1 << domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	return psc_wait(domain_num);
 }
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
index e07b64db9e..d4b0e9b163 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -18,10 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_K2HK_EVM
 static struct pll_init_data spl_pll_config[] = {
 	CORE_PLL_799,
 	TETRIS_PLL_500,
 };
+#endif
+
+#ifdef CONFIG_K2E_EVM
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_800,
+};
+#endif
 
 void spl_init_keystone_plls(void)
 {
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09612..745670e549 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -10,10 +10,13 @@
 #include <linux/linkage.h>
 #include <asm/gic.h>
 #include <asm/armv7.h>
+#include <asm/proc-armv/ptrace.h>
 
 .arch_extension sec
 .arch_extension virt
 
+	.pushsection ._secure.text, "ax"
+
 	.align	5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
@@ -22,43 +25,95 @@ _monitor_vectors:
 	adr pc, _secure_monitor
 	.word 0
 	.word 0
-	adr pc, _hyp_trap
+	.word 0
 	.word 0
 	.word 0
 
+.macro is_cpu_virt_capable	tmp
+	mrc	p15, 0, \tmp, c0, c1, 1		@ read ID_PFR1
+	and	\tmp, \tmp, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
+	cmp	\tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
+.endm
+
 /*
  * secure monitor handler
  * U-boot calls this "software interrupt" in start.S
  * This is executed on a "smc" instruction, we use a "smc #0" to switch
  * to non-secure state.
- * We use only r0 and r1 here, due to constraints in the caller.
+ * r0, r1, r2: passed to the callee
+ * ip: target PC
  */
 _secure_monitor:
-	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
-	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
-	orr	r1, r1, #0x31			@ enable NS, AW, FW bits
+#ifdef CONFIG_ARMV7_PSCI
+	ldr	r5, =_psci_vectors		@ Switch to the next monitor
+	mcr	p15, 0, r5, c12, c0, 1
+	isb
 
-#ifdef CONFIG_ARMV7_VIRT
-	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
-	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
-	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
-	orreq	r1, r1, #0x100			@ allow HVC instruction
+	@ Obtain a secure stack, and configure the PSCI backend
+	bl	psci_arch_init
 #endif
 
-	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
-
+	mrc	p15, 0, r5, c1, c1, 0		@ read SCR
+	bic	r5, r5, #0x4a			@ clear IRQ, EA, nET bits
+	orr	r5, r5, #0x31			@ enable NS, AW, FW bits
+						@ FIQ preserved for secure mode
+	mov	r6, #SVC_MODE			@ default mode is SVC
+	is_cpu_virt_capable r4
 #ifdef CONFIG_ARMV7_VIRT
-	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value
-	mcreq	p15, 4, r0, c12, c0, 0		@ write HVBAR
+	orreq	r5, r5, #0x100			@ allow HVC instruction
+	moveq	r6, #HYP_MODE			@ Enter the kernel as HYP
 #endif
 
-	movs	pc, lr				@ return to non-secure SVC
-
-_hyp_trap:
-	mrs	lr, elr_hyp	@ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
-	mov pc, lr				@ do no switch modes, but
-						@ return to caller
+	mcr	p15, 0, r5, c1, c1, 0		@ write SCR (with NS bit set)
+	isb
 
+	bne	1f
+
+	@ Reset CNTVOFF to 0 before leaving monitor mode
+	mrc	p15, 0, r4, c0, c1, 1		@ read ID_PFR1
+	ands	r4, r4, #CPUID_ARM_GENTIMER_MASK	@ test arch timer bits
+	movne	r4, #0
+	mcrrne	p15, 4, r4, r4, c14		@ Reset CNTVOFF to zero
+1:
+	mov	lr, ip
+	mov	ip, #(F_BIT | I_BIT | A_BIT)	@ Set A, I and F
+	tst	lr, #1				@ Check for Thumb PC
+	orrne	ip, ip, #T_BIT			@ Set T if Thumb
+	orr	ip, ip, r6			@ Slot target mode in
+	msr	spsr_cxfs, ip			@ Set full SPSR
+	movs	pc, lr				@ ERET to non-secure
+
+ENTRY(_do_nonsec_entry)
+	mov	ip, r0
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, r3
+	smc	#0
+ENDPROC(_do_nonsec_entry)
+
+.macro get_cbar_addr	addr
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
+#else
+	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
+	bfc	\addr, #0, #15			@ clear reserved bits
+#endif
+.endm
+
+.macro get_gicd_addr	addr
+	get_cbar_addr	\addr
+	add	\addr, \addr, #GIC_DIST_OFFSET	@ GIC dist i/f offset
+.endm
+
+.macro get_gicc_addr	addr, tmp
+	get_cbar_addr	\addr
+	is_cpu_virt_capable \tmp
+	movne	\tmp, #GIC_CPU_OFFSET_A9	@ GIC CPU offset for A9
+	moveq	\tmp, #GIC_CPU_OFFSET_A15	@ GIC CPU offset for A15/A7
+	add	\addr, \addr, \tmp
+.endm
+
+#ifndef CONFIG_ARMV7_PSCI
 /*
  * Secondary CPUs start here and call the code for the core specific parts
  * of the non-secure and HYP mode transition. The GIC distributor specific
@@ -66,31 +121,21 @@ _hyp_trap:
  * Then they go back to wfi and wait to be woken up by the kernel again.
  */
 ENTRY(_smp_pen)
-	mrs	r0, cpsr
-	orr	r0, r0, #0xc0
-	msr	cpsr, r0			@ disable interrupts
-	ldr	r1, =_start
-	mcr	p15, 0, r1, c12, c0, 0		@ set VBAR
+	cpsid	i
+	cpsid	f
 
 	bl	_nonsec_init
-	mov	r12, r0				@ save GICC address
-#ifdef CONFIG_ARMV7_VIRT
-	bl	_switch_to_hyp
-#endif
-
-	ldr	r1, [r12, #GICC_IAR]		@ acknowledge IPI
-	str	r1, [r12, #GICC_EOIR]		@ signal end of interrupt
 
 	adr	r0, _smp_pen			@ do not use this address again
 	b	smp_waitloop			@ wait for IPIs, board specific
 ENDPROC(_smp_pen)
+#endif
 
 /*
  * Switch a core to non-secure state.
  *
  *  1. initialize the GIC per-core interface
  *  2. allow coprocessor access in non-secure modes
- *  3. switch the cpu mode (by calling "smc #0")
  *
  * Called from smp_pen by secondary cores and directly by the BSP.
  * Do not assume that the stack is available and only use registers
@@ -100,38 +145,23 @@ ENDPROC(_smp_pen)
  * though, but we check this in C before calling this function.
  */
 ENTRY(_nonsec_init)
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	ldr	r2, =CONFIG_ARM_GIC_BASE_ADDRESS
-#else
-	mrc	p15, 4, r2, c15, c0, 0		@ read CBAR
-	bfc	r2, #0, #15			@ clear reserved bits
-#endif
-	add	r3, r2, #GIC_DIST_OFFSET	@ GIC dist i/f offset
+	get_gicd_addr	r3
+
 	mvn	r1, #0				@ all bits to 1
 	str	r1, [r3, #GICD_IGROUPRn]	@ allow private interrupts
 
-	mrc	p15, 0, r0, c0, c0, 0		@ read MIDR
-	ldr	r1, =MIDR_PRIMARY_PART_MASK
-	and	r0, r0, r1			@ mask out variant and revision
+	get_gicc_addr	r3, r1
 
-	ldr	r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
-	cmp	r0, r1				@ check for Cortex-A7
-
-	ldr	r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
-	cmpne	r0, r1				@ check for Cortex-A15
-
-	movne	r1, #GIC_CPU_OFFSET_A9		@ GIC CPU offset for A9
-	moveq	r1, #GIC_CPU_OFFSET_A15		@ GIC CPU offset for A15/A7
-	add	r3, r2, r1			@ r3 = GIC CPU i/f addr
-
-	mov	r1, #1				@ set GICC_CTLR[enable]
+	mov	r1, #3				@ Enable both groups
 	str	r1, [r3, #GICC_CTLR]		@ and clear all other bits
 	mov	r1, #0xff
 	str	r1, [r3, #GICC_PMR]		@ set priority mask register
 
+	mrc	p15, 0, r0, c1, c1, 2
 	movw	r1, #0x3fff
-	movt	r1, #0x0006
-	mcr	p15, 0, r1, c1, c1, 2		@ NSACR = all copros to non-sec
+	movt	r1, #0x0004
+	orr	r0, r0, r1
+	mcr	p15, 0, r0, c1, c1, 2		@ NSACR = all copros to non-sec
 
 /* The CNTFRQ register of the generic timer needs to be
  * programmed in secure state. Some primary bootloaders / firmware
@@ -149,21 +179,9 @@ ENTRY(_nonsec_init)
 
 	adr	r1, _monitor_vectors
 	mcr	p15, 0, r1, c12, c0, 1		@ set MVBAR to secure vectors
-
-	mrc	p15, 0, ip, c12, c0, 0		@ save secure copy of VBAR
-
 	isb
-	smc	#0				@ call into MONITOR mode
-
-	mcr	p15, 0, ip, c12, c0, 0		@ write non-secure copy of VBAR
-
-	mov	r1, #1
-	str	r1, [r3, #GICC_CTLR]		@ enable non-secure CPU i/f
-	add	r2, r2, #GIC_DIST_OFFSET
-	str	r1, [r2, #GICD_CTLR]		@ allow private interrupts
 
 	mov	r0, r3				@ return GICC address
-
 	bx	lr
 ENDPROC(_nonsec_init)
 
@@ -175,18 +193,10 @@ ENTRY(smp_waitloop)
 	ldr	r1, [r1]
 	cmp	r0, r1			@ make sure we dont execute this code
 	beq	smp_waitloop		@ again (due to a spurious wakeup)
-	mov	pc, r1
+	mov	r0, r1
+	b	_do_nonsec_entry
 ENDPROC(smp_waitloop)
 .weak smp_waitloop
 #endif
 
-ENTRY(_switch_to_hyp)
-	mov	r0, lr
-	mov	r1, sp				@ save SVC copy of LR and SP
-	isb
-	hvc #0			 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
-	mov	sp, r1
-	mov	lr, r0				@ restore SVC copy of LR and SP
-
-	bx	lr
-ENDPROC(_switch_to_hyp)
+	.popsection
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 5f50a19801..1b4477f469 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -123,7 +123,8 @@ void s_init(void)
 	hw_data_init();
 
 #ifdef CONFIG_SPL_BUILD
-	if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+	if (warm_reset() &&
+	    (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
 		force_emif_self_refresh();
 #endif
 	watchdog_init();
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 5bc7e1f19b..fc4290c3c4 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -87,9 +87,13 @@ void gpmc_init(void)
 						STNOR_GPMC_CONFIG6,
 						STNOR_GPMC_CONFIG7
 						};
-	u32 size = GPMC_SIZE_16M;
 	u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
+	u32 size =	(CONFIG_SYS_FLASH_SIZE  > 0x08000000) ? GPMC_SIZE_256M :
+	/* > 64MB */	((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+	/* > 32MB */	((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+	/* > 16MB */	((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+	/* min 16MB */	GPMC_SIZE_16M)));
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 /* configure GPMC for NAND */
 	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
 						M_NAND_GPMC_CONFIG2,
@@ -99,8 +103,9 @@ void gpmc_init(void)
 						M_NAND_GPMC_CONFIG6,
 						0
 						};
-	u32 size = GPMC_SIZE_256M;
 	u32 base = CONFIG_SYS_NAND_BASE;
+	u32 size = GPMC_SIZE_16M;
+
 #elif defined(CONFIG_CMD_ONENAND)
 	const u32 gpmc_regs[GPMC_MAX_REG] = {	ONENAND_GPMC_CONFIG1,
 						ONENAND_GPMC_CONFIG2,
@@ -110,8 +115,8 @@ void gpmc_init(void)
 						ONENAND_GPMC_CONFIG6,
 						0
 						};
-	u32 base = PISMO1_ONEN_BASE;
-	u32 size = PISMO1_ONEN_SIZE;
+	u32 size = GPMC_SIZE_128M;
+	u32 base = CONFIG_SYS_ONENAND_BASE;
 #else
 	const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
 	u32 size = 0;
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644
index 1832affa5b..0000000000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- *     Richard Woodruff <r-woodruff2@ti.com>
- *     Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
-	ONENAND_GPMC_CONFIG1,
-	ONENAND_GPMC_CONFIG2,
-	ONENAND_GPMC_CONFIG3,
-	ONENAND_GPMC_CONFIG4,
-	ONENAND_GPMC_CONFIG5,
-	ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/********************************************************
- *  mem_ok() - test used to see if timings are correct
- *             for a part. Helps in guessing which part
- *             we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
-	u32 val1, val2, addr;
-	u32 pattern = 0x12345678;
-
-	addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
-	writel(0x0, addr + 0x400);	/* clear pos A */
-	writel(pattern, addr);		/* pattern to pos B */
-	writel(0x0, addr + 4);		/* remove pattern off the bus */
-	val1 = readl(addr + 0x400);	/* get pos A value */
-	val2 = readl(addr);		/* get val2 */
-	writel(0x0, addr + 0x400);	/* clear pos A */
-
-	if ((val1 != 0) || (val2 != pattern))	/* see if pos A val changed */
-		return 0;
-	else
-		return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size)
-{
-	writel(0, &cs->config7);
-	sdelay(1000);
-	/* Delay for settling */
-	writel(gpmc_config[0], &cs->config1);
-	writel(gpmc_config[1], &cs->config2);
-	writel(gpmc_config[2], &cs->config3);
-	writel(gpmc_config[3], &cs->config4);
-	writel(gpmc_config[4], &cs->config5);
-	writel(gpmc_config[5], &cs->config6);
-
-	/*
-	 * Enable the config.  size is the CS size and goes in
-	 * bits 11:8.  We set bit 6 to enable this CS and the base
-	 * address goes into bits 5:0.
-	 */
-	 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
-				 ((base >> 24) & GPMC_BASEADDR_MASK),
-				 &cs->config7);
-	sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	/* putting a blanket check on GPMC based on ZeBu for now */
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
-	const u32 *gpmc_config = NULL;
-	u32 base = 0;
-	u32 size = 0;
-#endif
-	u32 config = 0;
-
-	/* global settings */
-	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-	config = readl(&gpmc_cfg->config);
-	config &= (~0xf00);
-	writel(config, &gpmc_cfg->config);
-
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 * It conflicts with our MPDB (both at 0x08000000)
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-	sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND)	/* CS 0 */
-	gpmc_config = gpmc_m_nand;
-
-	base = PISMO1_NAND_BASE;
-	size = PISMO1_NAND_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	gpmc_config = gpmc_onenand;
-	base = PISMO1_ONEN_BASE;
-	size = PISMO1_ONEN_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-}
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
new file mode 100644
index 0000000000..bf11a34e54
--- /dev/null
+++ b/arch/arm/cpu/armv7/psci.S
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2013,2014 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension	sec
+
+	.align	5
+	.globl _psci_vectors
+_psci_vectors:
+	b	default_psci_vector	@ reset
+	b	default_psci_vector	@ undef
+	b	_smc_psci		@ smc
+	b	default_psci_vector	@ pabort
+	b	default_psci_vector	@ dabort
+	b	default_psci_vector	@ hyp
+	b	default_psci_vector	@ irq
+	b	psci_fiq_enter		@ fiq
+
+ENTRY(psci_fiq_enter)
+	movs	pc, lr
+ENDPROC(psci_fiq_enter)
+.weak psci_fiq_enter
+
+ENTRY(default_psci_vector)
+	movs	pc, lr
+ENDPROC(default_psci_vector)
+.weak default_psci_vector
+
+ENTRY(psci_cpu_suspend)
+ENTRY(psci_cpu_off)
+ENTRY(psci_cpu_on)
+ENTRY(psci_migrate)
+	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
+	mov	pc, lr
+ENDPROC(psci_migrate)
+ENDPROC(psci_cpu_on)
+ENDPROC(psci_cpu_off)
+ENDPROC(psci_cpu_suspend)
+.weak psci_cpu_suspend
+.weak psci_cpu_off
+.weak psci_cpu_on
+.weak psci_migrate
+
+_psci_table:
+	.word	ARM_PSCI_FN_CPU_SUSPEND
+	.word	psci_cpu_suspend
+	.word	ARM_PSCI_FN_CPU_OFF
+	.word	psci_cpu_off
+	.word	ARM_PSCI_FN_CPU_ON
+	.word	psci_cpu_on
+	.word	ARM_PSCI_FN_MIGRATE
+	.word	psci_migrate
+	.word	0
+	.word	0
+
+_smc_psci:
+	push	{r4-r7,lr}
+
+	@ Switch to secure
+	mrc	p15, 0, r7, c1, c1, 0
+	bic	r4, r7, #1
+	mcr	p15, 0, r4, c1, c1, 0
+	isb
+
+	adr	r4, _psci_table
+1:	ldr	r5, [r4]		@ Load PSCI function ID
+	ldr	r6, [r4, #4]		@ Load target PC
+	cmp	r5, #0			@ If reach the end, bail out
+	moveq	r0, #ARM_PSCI_RET_INVAL	@ Return -2 (Invalid)
+	beq	2f
+	cmp	r0, r5			@ If not matching, try next entry
+	addne	r4, r4, #8
+	bne	1b
+
+	blx	r6			@ Execute PSCI function
+
+	@ Switch back to non-secure
+2:	mcr	p15, 0, r7, c1, c1, 0
+
+	pop	{r4-r7, lr}
+	movs	pc, lr			@ Return to the kernel
+
+	.popsection
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index fad004ca64..dd7de41082 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 7a7c97d791..b98137e86a 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -53,6 +53,7 @@ static const struct {
 	{ 0x40, "R8A7740" },
 	{ 0x45, "R8A7790" },
 	{ 0x47, "R8A7791" },
+	{ 0x4C, "R8A7794" },
 	{ 0x0, "CPU" },
 };
 
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
new file mode 100644
index 0000000000..e123663333
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
@@ -0,0 +1,1513 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+ *     This file is r8a7794 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_26_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+#define CPU_28_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_6_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
+ *  GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
+ *  GP6[29]),GP6[30],GP6[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx)			\
+	CPU_32_PORT(fn, pfx##_0_, sfx),			\
+	CPU_26_PORT(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),			\
+	CPU_32_PORT(fn, pfx##_3_, sfx),			\
+	CPU_32_PORT(fn, pfx##_4_, sfx),			\
+	CPU_28_PORT(fn, pfx##_5_, sfx),			\
+	CPU_26_PORT(fn, pfx##_6_, sfx)
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
+	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
+	FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
+	FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
+	FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
+	FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
+	FN_IP2_17_16,
+
+	/* GPSR1 */
+	FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
+	FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
+	FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
+	FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
+	FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
+
+	/* GPSR2 */
+	FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
+	FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
+	FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
+	FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
+	FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
+	FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
+	FN_IP6_5_4, FN_IP6_7_6,
+
+	/* GPSR3 */
+	FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
+	FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
+	FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
+	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
+	FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
+	FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
+	FN_IP8_22_20,
+
+	/* GPSR4 */
+	FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
+	FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
+	FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
+	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+	FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
+	FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
+	FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
+
+	/* GPSR5 */
+	FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+	FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
+	FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
+	FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
+	FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
+	FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
+
+	/* GPSR6 */
+	FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
+	FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
+	FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
+	FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
+	FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
+	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+	FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
+	FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
+	FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
+	FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
+	FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
+	FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
+	FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
+	FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
+	FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
+	FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
+	FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
+	FN_ADIDATA, FN_AD_DI,
+
+	/* IPSR7 */
+	FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
+	FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
+	FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
+	FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+	FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
+	FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+	FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
+	FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
+	FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
+	FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
+	FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
+	FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
+	FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
+
+	/* IPSR8 */
+	FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
+	FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
+	FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
+	FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
+	FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+	FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
+	FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
+	FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+	FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
+	FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
+	FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
+	FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
+	FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
+	FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
+	FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+	FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
+	FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
+	FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
+	FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+	FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
+	FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
+	FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
+	FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
+	FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+	FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+	FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+	FN_ADICLK_B, FN_AD_CLK_B,
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	/* MOD_SEL */
+	FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+	FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
+	FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
+	FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
+	FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
+	FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
+	FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
+	FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
+	FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
+	FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
+	FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+	FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
+	FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
+	FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+
+	/* MOD_SEL2 */
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
+	FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
+	FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
+	FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
+	FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
+	FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
+	FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
+	FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
+	FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+	FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+	FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
+	FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+	FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
+	FN_SEL_RDS_2, FN_SEL_RDS_3,
+
+	/* MOD_SEL3 */
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
+	FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+	FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
+	FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
+	FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
+	FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
+	FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
+	FN_SEL_SSI9_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
+
+	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+
+	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
+	SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
+
+	SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
+	SD1_DATA2_MARK, SD1_DATA3_MARK,
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
+	DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
+	CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
+	AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
+	VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
+	AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
+	VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
+	AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
+	I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
+	VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
+	AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+	IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
+	I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
+	VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
+	ADIDATA_MARK, AD_DI_MARK,
+
+	/* IPSR7 */
+	ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
+	AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
+	MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
+	AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
+	CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+	ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
+	AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
+	MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+	ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
+	SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
+	IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
+	VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
+	SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
+	AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
+	SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
+	DREQ0_N_MARK, SCIFB1_RXD_MARK,
+
+	/* IPSR8 */
+	ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
+	AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
+	I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
+	HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
+	AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
+	SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
+	HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
+	AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
+	HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
+	I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
+	AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
+	SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
+	CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
+	DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
+	I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
+	TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
+	I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
+	FMCLK_C_MARK, RDS_CLK_MARK,
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
+	CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
+	DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
+	SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+	SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
+	DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
+	SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+	CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
+	DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
+	DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
+	AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
+	MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
+	PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+	ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
+	PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_DATA(A2_MARK, FN_A2),
+	PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
+	PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
+	PINMUX_DATA(DACK0_MARK, FN_DACK0),
+	PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+	PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
+	PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
+	PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
+	PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
+	PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
+	PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
+	PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
+	PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
+	PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
+	PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
+	PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
+	PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
+	PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
+	PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
+	PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
+	PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
+	PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+	PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
+	PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
+	PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
+	PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
+	PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
+	PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
+	PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
+	PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
+	PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
+	PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
+	PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
+	PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
+	PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
+	PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
+	PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
+	PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
+	PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
+	PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
+	PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
+	PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
+	PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
+	PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
+	PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
+	PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
+	PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
+	PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
+	PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
+	PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
+	PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
+	PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
+	PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
+
+	/* IPSR7 */
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
+	PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
+	PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
+	PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
+	PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
+	PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
+	PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
+	PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
+	PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
+	PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
+	PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
+	PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
+	PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
+
+	/* IPSR8 */
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
+	PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
+	PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
+	PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
+	PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+	PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
+	PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
+	PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
+	PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
+	PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
+	PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
+	PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
+	PINMUX_IPSR_DATA(IP8_19_17, PWM5),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
+	PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
+	PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
+	PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
+	PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
+	PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
+	PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
+	PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
+	PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+	PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
+	PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
+	PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+	PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
+	PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
+	PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
+	PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
+	PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
+	PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
+	PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+	PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
+	PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+	PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
+	PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
+	PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
+	PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
+	PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
+	PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
+	PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
+	PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
+	PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
+	PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
+	PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
+	GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
+	GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
+	GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
+	GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
+	GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
+	GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use
+	 */
+
+	/* IPSR6 */
+	GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
+	GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
+	GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
+	GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
+	GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
+	GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
+	GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
+	GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
+	GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
+	GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
+	GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
+	GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
+	GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
+	GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
+	GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
+	GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
+	GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
+	GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
+	GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
+
+	/* IPSR7 */
+	GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
+	GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
+	GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
+	GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
+	GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
+	GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
+	GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
+	GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
+	GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
+	GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
+	GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
+	GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
+	GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
+	GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
+	GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
+	GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
+	GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
+	GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
+	GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
+	GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
+	GPIO_FN(SCIFB1_RXD),
+
+	/* IPSR8 */
+	GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
+	GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
+	GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
+	GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
+	GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
+	GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
+	GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
+	GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
+	GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
+	GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
+	GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
+	GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
+	GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
+	GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
+	GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
+	GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
+	GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
+	GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
+	GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
+	GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
+	GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
+	GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
+	GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
+	GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
+	GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
+	GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
+	GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
+	GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
+	GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
+	GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
+	GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
+	GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
+	GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
+	GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
+	GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
+	GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
+	GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
+	GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
+	GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
+	GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
+	GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP2_17_16,
+		GP_0_30_FN, FN_IP2_15_14,
+		GP_0_29_FN, FN_IP2_13_12,
+		GP_0_28_FN, FN_IP2_11_10,
+		GP_0_27_FN, FN_IP2_9_8,
+		GP_0_26_FN, FN_IP2_7_6,
+		GP_0_25_FN, FN_IP2_5_4,
+		GP_0_24_FN, FN_IP2_3_2,
+		GP_0_23_FN, FN_IP2_1_0,
+		GP_0_22_FN, FN_IP1_31_30,
+		GP_0_21_FN, FN_IP1_29_28,
+		GP_0_20_FN, FN_IP1_27,
+		GP_0_19_FN, FN_IP1_26,
+		GP_0_18_FN, FN_A2,
+		GP_0_17_FN, FN_IP1_24,
+		GP_0_16_FN, FN_IP1_23_22,
+		GP_0_15_FN, FN_IP1_21_20,
+		GP_0_14_FN, FN_IP1_19_18,
+		GP_0_13_FN, FN_IP1_17_15,
+		GP_0_12_FN, FN_IP1_14_13,
+		GP_0_11_FN, FN_IP1_12_11,
+		GP_0_10_FN, FN_IP1_10_8,
+		GP_0_9_FN, FN_IP1_7_6,
+		GP_0_8_FN, FN_IP1_5_4,
+		GP_0_7_FN, FN_IP1_3_2,
+		GP_0_6_FN, FN_IP1_1_0,
+		GP_0_5_FN, FN_IP0_31_30,
+		GP_0_4_FN, FN_IP0_29_28,
+		GP_0_3_FN, FN_IP0_27_26,
+		GP_0_2_FN, FN_IP0_25,
+		GP_0_1_FN, FN_IP0_24,
+		GP_0_0_FN, FN_IP0_23_22, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_FN, FN_DACK0,
+		GP_1_24_FN, FN_IP7_31,
+		GP_1_23_FN, FN_IP4_1_0,
+		GP_1_22_FN, FN_WE1_N,
+		GP_1_21_FN, FN_WE0_N,
+		GP_1_20_FN, FN_IP3_31,
+		GP_1_19_FN, FN_IP3_30,
+		GP_1_18_FN, FN_IP3_29_27,
+		GP_1_17_FN, FN_IP3_26_24,
+		GP_1_16_FN, FN_IP3_23_21,
+		GP_1_15_FN, FN_IP3_20_18,
+		GP_1_14_FN, FN_IP3_17_15,
+		GP_1_13_FN, FN_IP3_14_13,
+		GP_1_12_FN, FN_IP3_12,
+		GP_1_11_FN, FN_IP3_11,
+		GP_1_10_FN, FN_IP3_10,
+		GP_1_9_FN, FN_IP3_9_8,
+		GP_1_8_FN, FN_IP3_7_6,
+		GP_1_7_FN, FN_IP3_5_4,
+		GP_1_6_FN, FN_IP3_3_2,
+		GP_1_5_FN, FN_IP3_1_0,
+		GP_1_4_FN, FN_IP2_31_30,
+		GP_1_3_FN, FN_IP2_29_27,
+		GP_1_2_FN, FN_IP2_26_24,
+		GP_1_1_FN, FN_IP2_23_21,
+		GP_1_0_FN, FN_IP2_20_18, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_IP6_7_6,
+		GP_2_30_FN, FN_IP6_5_4,
+		GP_2_29_FN, FN_IP6_3_2,
+		GP_2_28_FN, FN_IP6_1_0,
+		GP_2_27_FN, FN_IP5_31_30,
+		GP_2_26_FN, FN_IP5_29_28,
+		GP_2_25_FN, FN_IP5_27_26,
+		GP_2_24_FN, FN_IP5_25_24,
+		GP_2_23_FN, FN_IP5_23_22,
+		GP_2_22_FN, FN_IP5_21_20,
+		GP_2_21_FN, FN_IP5_19_18,
+		GP_2_20_FN, FN_IP5_17_16,
+		GP_2_19_FN, FN_IP5_15_14,
+		GP_2_18_FN, FN_IP5_13_12,
+		GP_2_17_FN, FN_IP5_11_9,
+		GP_2_16_FN, FN_IP5_8_6,
+		GP_2_15_FN, FN_IP5_5_4,
+		GP_2_14_FN, FN_IP5_3_2,
+		GP_2_13_FN, FN_IP5_1_0,
+		GP_2_12_FN, FN_IP4_31_30,
+		GP_2_11_FN, FN_IP4_29_28,
+		GP_2_10_FN, FN_IP4_27_26,
+		GP_2_9_FN, FN_IP4_25_23,
+		GP_2_8_FN, FN_IP4_22_20,
+		GP_2_7_FN, FN_IP4_19_18,
+		GP_2_6_FN, FN_IP4_17_16,
+		GP_2_5_FN, FN_IP4_15_14,
+		GP_2_4_FN, FN_IP4_13_12,
+		GP_2_3_FN, FN_IP4_11_10,
+		GP_2_2_FN, FN_IP4_9_8,
+		GP_2_1_FN, FN_IP4_7_5,
+		GP_2_0_FN, FN_IP4_4_2 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP8_22_20,
+		GP_3_30_FN, FN_IP8_19_17,
+		GP_3_29_FN, FN_IP8_16_15,
+		GP_3_28_FN, FN_IP8_14_12,
+		GP_3_27_FN, FN_IP8_11_9,
+		GP_3_26_FN, FN_IP8_8_6,
+		GP_3_25_FN, FN_IP8_5_3,
+		GP_3_24_FN, FN_IP8_2_0,
+		GP_3_23_FN, FN_IP7_29_27,
+		GP_3_22_FN, FN_IP7_26_24,
+		GP_3_21_FN, FN_IP7_23_21,
+		GP_3_20_FN, FN_IP7_20_18,
+		GP_3_19_FN, FN_IP7_17_15,
+		GP_3_18_FN, FN_IP7_14_12,
+		GP_3_17_FN, FN_IP7_11_9,
+		GP_3_16_FN, FN_IP7_8_6,
+		GP_3_15_FN, FN_IP7_5_3,
+		GP_3_14_FN, FN_IP7_2_0,
+		GP_3_13_FN, FN_IP6_31_29,
+		GP_3_12_FN, FN_IP6_28_26,
+		GP_3_11_FN, FN_IP6_25_23,
+		GP_3_10_FN, FN_IP6_22_20,
+		GP_3_9_FN, FN_IP6_19_17,
+		GP_3_8_FN, FN_IP6_16,
+		GP_3_7_FN, FN_IP6_15,
+		GP_3_6_FN, FN_IP6_14,
+		GP_3_5_FN, FN_IP6_13,
+		GP_3_4_FN, FN_IP6_12,
+		GP_3_3_FN, FN_IP6_11,
+		GP_3_2_FN, FN_IP6_10,
+		GP_3_1_FN, FN_IP6_9,
+		GP_3_0_FN, FN_IP6_8 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP11_17_16,
+		GP_4_30_FN, FN_IP11_15_14,
+		GP_4_29_FN, FN_IP11_13_11,
+		GP_4_28_FN, FN_IP11_10_8,
+		GP_4_27_FN, FN_IP11_7_6,
+		GP_4_26_FN, FN_IP11_5_3,
+		GP_4_25_FN, FN_IP11_2_0,
+		GP_4_24_FN, FN_IP10_31_30,
+		GP_4_23_FN, FN_IP10_29_27,
+		GP_4_22_FN, FN_IP10_26_24,
+		GP_4_21_FN, FN_IP10_23_21,
+		GP_4_20_FN, FN_IP10_20_18,
+		GP_4_19_FN, FN_IP10_17_15,
+		GP_4_18_FN, FN_IP10_14_12,
+		GP_4_17_FN, FN_IP10_11_9,
+		GP_4_16_FN, FN_IP10_8_6,
+		GP_4_15_FN, FN_IP10_5_3,
+		GP_4_14_FN, FN_IP10_2_0,
+		GP_4_13_FN, FN_IP9_30_28,
+		GP_4_12_FN, FN_IP9_27_25,
+		GP_4_11_FN, FN_IP9_24_22,
+		GP_4_10_FN, FN_IP9_21_19,
+		GP_4_9_FN, FN_IP9_18_17,
+		GP_4_8_FN, FN_IP9_16_15,
+		GP_4_7_FN, FN_IP9_14_12,
+		GP_4_6_FN, FN_IP9_11_9,
+		GP_4_5_FN, FN_IP9_8_6,
+		GP_4_4_FN, FN_IP9_5_3,
+		GP_4_3_FN, FN_IP9_2_0,
+		GP_4_2_FN, FN_IP8_31_29,
+		GP_4_1_FN, FN_IP8_28_26,
+		GP_4_0_FN, FN_IP8_25_23 }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_27_FN, FN_USB1_OVC,
+		GP_5_26_FN, FN_USB1_PWEN,
+		GP_5_25_FN, FN_USB0_OVC,
+		GP_5_24_FN, FN_USB0_PWEN,
+		GP_5_23_FN, FN_IP13_26_24,
+		GP_5_22_FN, FN_IP13_23_21,
+		GP_5_21_FN, FN_IP13_20_18,
+		GP_5_20_FN, FN_IP13_17_15,
+		GP_5_19_FN, FN_IP13_14_12,
+		GP_5_18_FN, FN_IP13_11_9,
+		GP_5_17_FN, FN_IP13_8_6,
+		GP_5_16_FN, FN_IP13_5_3,
+		GP_5_15_FN, FN_IP13_2_0,
+		GP_5_14_FN, FN_IP12_29_27,
+		GP_5_13_FN, FN_IP12_26_24,
+		GP_5_12_FN, FN_IP12_23_21,
+		GP_5_11_FN, FN_IP12_20_18,
+		GP_5_10_FN, FN_IP12_17_15,
+		GP_5_9_FN, FN_IP12_14_13,
+		GP_5_8_FN, FN_IP12_12_11,
+		GP_5_7_FN, FN_IP12_10_9,
+		GP_5_6_FN, FN_IP12_8_6,
+		GP_5_5_FN, FN_IP12_5_3,
+		GP_5_4_FN, FN_IP12_2_0,
+		GP_5_3_FN, FN_IP11_29_27,
+		GP_5_2_FN, FN_IP11_26_24,
+		GP_5_1_FN, FN_IP11_23_21,
+		GP_5_0_FN, FN_IP11_20_18 }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_25_FN, FN_IP0_21_20,
+		GP_6_24_FN, FN_IP0_19_18,
+		GP_6_23_FN, FN_IP0_17,
+		GP_6_22_FN, FN_IP0_16,
+		GP_6_21_FN, FN_IP0_15,
+		GP_6_20_FN, FN_IP0_14,
+		GP_6_19_FN, FN_IP0_13,
+		GP_6_18_FN, FN_IP0_12,
+		GP_6_17_FN, FN_IP0_11,
+		GP_6_16_FN, FN_IP0_10,
+		GP_6_15_FN, FN_IP0_9_8,
+		GP_6_14_FN, FN_IP0_0,
+		GP_6_13_FN, FN_SD1_DATA3,
+		GP_6_12_FN, FN_SD1_DATA2,
+		GP_6_11_FN, FN_SD1_DATA1,
+		GP_6_10_FN, FN_SD1_DATA0,
+		GP_6_9_FN, FN_SD1_CMD,
+		GP_6_8_FN, FN_SD1_CLK,
+		GP_6_7_FN, FN_SD0_WP,
+		GP_6_6_FN, FN_SD0_CD,
+		GP_6_5_FN, FN_SD0_DATA3,
+		GP_6_4_FN, FN_SD0_DATA2,
+		GP_6_3_FN, FN_SD0_DATA1,
+		GP_6_2_FN, FN_SD0_DATA0,
+		GP_6_1_FN, FN_SD0_CMD,
+		GP_6_0_FN, FN_SD0_CLK }
+	},
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+			     3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+			     2, 2) {
+		/* IP6_31_29 [3] */
+		FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
+		FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
+		/* IP6_28_26 [3] */
+		FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
+		FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
+		/* IP6_25_23 [3] */
+		FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
+		FN_AVB_COL, 0, 0, 0,
+		/* IP6_22_20 [3] */
+		FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
+		FN_AVB_RX_ER, 0, 0, 0,
+		/* IP6_19_17 [3] */
+		FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
+		FN_AVB_RXD7, 0, 0, 0,
+		/* IP6_16 [1] */
+		FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+		/* IP6_15 [1] */
+		FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+		/* IP6_14 [1] */
+		FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+		/* IP6_13 [1] */
+		FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+		/* IP6_12 [1] */
+		FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+		/* IP6_11 [1] */
+		FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+		/* IP6_10 [1] */
+		FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+		/* IP6_9 [1] */
+		FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+		/* IP6_8 [1] */
+		FN_VI0_CLK, FN_AVB_RX_CLK,
+		/* IP6_7_6 [2] */
+		FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
+		/* IP6_5_4 [2] */
+		FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
+		/* IP6_3_2 [2] */
+		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+		/* IP6_1_0 [2] */
+		FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+			     1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+		/* IP7_31 [1] */
+		FN_DREQ0_N, FN_SCIFB1_RXD,
+		/* IP7_30 [1] */
+		0, 0,
+		/* IP7_29_27 [3] */
+		FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
+		FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
+		/* IP7_26_24 [3] */
+		FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
+		FN_SSI_SCK6_B, 0, 0, 0,
+		/* IP7_23_21 [3] */
+		FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
+		FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
+		/* IP7_20_18 [3] */
+		FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
+		FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
+		/* IP7_17_15 [3] */
+		FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
+		FN_SSI_SCK5_B, 0, 0, 0,
+		/* IP7_14_12 [3] */
+		FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+		FN_AVB_TXD4, FN_ADICHS2, 0, 0,
+		/* IP7_11_9 [3] */
+		FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
+		FN_AVB_TXD3, FN_ADICHS1, 0, 0,
+		/* IP7_8_6 [3] */
+		FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
+		FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
+		/* IP7_5_3 [3] */
+		FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
+		FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
+		/* IP7_2_0 [3] */
+		FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
+		FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+			     3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+		/* IP8_31_29 [3] */
+		FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+		FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+		/* IP8_28_26 [3] */
+		FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+		FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
+		/* IP8_25_23 [3] */
+		FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
+		FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
+		/* IP8_22_20 [3] */
+		FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
+		FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
+		/* IP8_19_17 [3] */
+		FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
+		FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
+		/* IP8_16_15 [2] */
+		FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+		/* IP8_14_12 [3] */
+		FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+		FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
+		/* IP8_11_9 [3] */
+		FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+		FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
+		/* IP8_8_6 [3] */
+		FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
+		FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
+		/* IP8_5_3 [3] */
+		FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
+		FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
+		/* IP8_2_0 [3] */
+		FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
+		FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+	},
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+			     2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+		/* IP11_31_30 [2] */
+		0, 0, 0, 0,
+		/* IP11_29_27 [3] */
+		FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+		FN_AD_CLK_B, 0, 0, 0,
+		/* IP11_26_24 [3] */
+		FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+		FN_AD_DO_B, 0, 0, 0,
+		/* IP11_23_21 [3] */
+		FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+		FN_AD_DI_B, FN_PCMWE_N, 0, 0,
+		/* IP11_20_18 [3] */
+		FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
+		FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
+		/* IP11_17_16 [2] */
+		FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
+		/* IP11_15_14 [2] */
+		FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
+		/* IP11_13_11 [3] */
+		FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+		FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
+		/* IP11_10_8 [3] */
+		FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
+		FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
+		/* IP11_7_6 [2] */
+		FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
+		FN_CAN_DEBUGOUT13,
+		/* IP11_5_3 [3] */
+		FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+		FN_CAN_DEBUGOUT12, 0, 0, 0,
+		/* IP11_2_0 [3] */
+		FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+		FN_CAN_DEBUGOUT11, 0, 0, 0, }
+	},
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+
+	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+			     2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
+			     2, 1) {
+		/* SEL_ADG [2] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+		/* SEL_ADI [1] */
+		FN_SEL_ADI_0, FN_SEL_ADI_1,
+		/* SEL_CAN [2] */
+		FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+		/* SEL_DARC [3] */
+		FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+		FN_SEL_DARC_4, 0, 0, 0,
+		/* SEL_DR0 [1] */
+		FN_SEL_DR0_0, FN_SEL_DR0_1,
+		/* SEL_DR1 [1] */
+		FN_SEL_DR1_0, FN_SEL_DR1_1,
+		/* SEL_DR2 [1] */
+		FN_SEL_DR2_0, FN_SEL_DR2_1,
+		/* SEL_DR3 [1] */
+		FN_SEL_DR3_0, FN_SEL_DR3_1,
+		/* SEL_ETH [1] */
+		FN_SEL_ETH_0, FN_SEL_ETH_1,
+		/* SLE_FSN [1] */
+		FN_SEL_FSN_0, FN_SEL_FSN_1,
+		/* SEL_IC200 [3] */
+		FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+		FN_SEL_I2C00_4, 0, 0, 0,
+		/* SEL_I2C01 [3] */
+		FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+		FN_SEL_I2C01_4, 0, 0, 0,
+		/* SEL_I2C02 [3] */
+		FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+		FN_SEL_I2C02_4, 0, 0, 0,
+		/* SEL_I2C03 [3] */
+		FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+		FN_SEL_I2C03_4, 0, 0, 0,
+		/* SEL_I2C04 [3] */
+		FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+		FN_SEL_I2C04_4, 0, 0, 0,
+		/* SEL_IIC00 [2] */
+		FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
+		/* SEL_AVB [1] */
+		FN_SEL_AVB_0, FN_SEL_AVB_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+			     2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
+			     2, 2, 2, 1, 1, 2) {
+		/* SEL_IEB [2] */
+		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+		/* SEL_IIC0 [2] */
+		FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
+		/* SEL_LBS [1] */
+		FN_SEL_LBS_0, FN_SEL_LBS_1,
+		/* SEL_MSI1 [1] */
+		FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+		/* SEL_MSI2 [1] */
+		FN_SEL_MSI2_0, FN_SEL_MSI2_1,
+		/* SEL_RAD [1] */
+		FN_SEL_RAD_0, FN_SEL_RAD_1,
+		/* SEL_RCN [1] */
+		FN_SEL_RCN_0, FN_SEL_RCN_1,
+		/* SEL_RSP [1] */
+		FN_SEL_RSP_0, FN_SEL_RSP_1,
+		/* SEL_SCIFA0 [2] */
+		FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
+		FN_SEL_SCIFA0_3,
+		/* SEL_SCIFA1 [2] */
+		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+		/* SEL_SCIFA2 [1] */
+		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+		/* SEL_SCIFA3 [1] */
+		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+		/* SEL_SCIFA4 [2] */
+		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+		FN_SEL_SCIFA4_3,
+		/* SEL_SCIFA5 [2] */
+		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+		FN_SEL_SCIFA5_3,
+		/* SEL_SPDM [1] */
+		FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+		/* SEL_TMU [1] */
+		FN_SEL_TMU_0, FN_SEL_TMU_1,
+		/* SEL_TSIF0 [2] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		/* SEL_CAN0 [2] */
+		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+		/* SEL_CAN1 [2] */
+		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+		/* SEL_HSCIF0 [1] */
+		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+		/* SEL_HSCIF1 [1] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+		/* SEL_RDS [2] */
+		FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+			     2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+		/* SEL_SCIF0 [2] */
+		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+		/* SEL_SCIF1 [2] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
+		/* SEL_SCIF2 [2] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
+		/* SEL_SCIF3 [1] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+		/* SEL_SCIF4 [3] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+		FN_SEL_SCIF4_4, 0, 0, 0,
+		/* SEL_SCIF5 [2] */
+		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+		/* SEL_SSI1 [1] */
+		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+		/* SEL_SSI2 [1] */
+		FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+		/* SEL_SSI4 [1] */
+		FN_SEL_SSI4_0, FN_SEL_SSI4_1,
+		/* SEL_SSI5 [1] */
+		FN_SEL_SSI5_0, FN_SEL_SSI5_1,
+		/* SEL_SSI6 [1] */
+		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+		/* SEL_SSI7 [1] */
+		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+		/* SEL_SSI8 [1] */
+		FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+		/* SEL_SSI9 [1] */
+		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* RESEVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_27_IN, GP_5_27_OUT,
+		GP_5_26_IN, GP_5_26_OUT,
+		GP_5_25_IN, GP_5_25_OUT,
+		GP_5_24_IN, GP_5_24_OUT,
+		GP_5_23_IN, GP_5_23_OUT,
+		GP_5_22_IN, GP_5_22_OUT,
+		GP_5_21_IN, GP_5_21_OUT,
+		GP_5_20_IN, GP_5_20_OUT,
+		GP_5_19_IN, GP_5_19_OUT,
+		GP_5_18_IN, GP_5_18_OUT,
+		GP_5_17_IN, GP_5_17_OUT,
+		GP_5_16_IN, GP_5_16_OUT,
+		GP_5_15_IN, GP_5_15_OUT,
+		GP_5_14_IN, GP_5_14_OUT,
+		GP_5_13_IN, GP_5_13_OUT,
+		GP_5_12_IN, GP_5_12_OUT,
+		GP_5_11_IN, GP_5_11_OUT,
+		GP_5_10_IN, GP_5_10_OUT,
+		GP_5_9_IN, GP_5_9_OUT,
+		GP_5_8_IN, GP_5_8_OUT,
+		GP_5_7_IN, GP_5_7_OUT,
+		GP_5_6_IN, GP_5_6_OUT,
+		GP_5_5_IN, GP_5_5_OUT,
+		GP_5_4_IN, GP_5_4_OUT,
+		GP_5_3_IN, GP_5_3_OUT,
+		GP_5_2_IN, GP_5_2_OUT,
+		GP_5_1_IN, GP_5_1_OUT,
+		GP_5_0_IN, GP_5_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_25_IN, GP_6_25_OUT,
+		GP_6_24_IN, GP_6_24_OUT,
+		GP_6_23_IN, GP_6_23_OUT,
+		GP_6_22_IN, GP_6_22_OUT,
+		GP_6_21_IN, GP_6_21_OUT,
+		GP_6_20_IN, GP_6_20_OUT,
+		GP_6_19_IN, GP_6_19_OUT,
+		GP_6_18_IN, GP_6_18_OUT,
+		GP_6_17_IN, GP_6_17_OUT,
+		GP_6_16_IN, GP_6_16_OUT,
+		GP_6_15_IN, GP_6_15_OUT,
+		GP_6_14_IN, GP_6_14_OUT,
+		GP_6_13_IN, GP_6_13_OUT,
+		GP_6_12_IN, GP_6_12_OUT,
+		GP_6_11_IN, GP_6_11_OUT,
+		GP_6_10_IN, GP_6_10_OUT,
+		GP_6_9_IN, GP_6_9_OUT,
+		GP_6_8_IN, GP_6_8_OUT,
+		GP_6_7_IN, GP_6_7_OUT,
+		GP_6_6_IN, GP_6_6_OUT,
+		GP_6_5_IN, GP_6_5_OUT,
+		GP_6_4_IN, GP_6_4_OUT,
+		GP_6_3_IN, GP_6_3_OUT,
+		GP_6_2_IN, GP_6_2_OUT,
+		GP_6_1_IN, GP_6_1_OUT,
+		GP_6_0_IN, GP_6_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+		0, 0, 0, 0,
+		GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
+		GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
+		GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
+		GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_6_25_DATA, GP_6_24_DATA,
+		GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
+		GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
+		GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
+		GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
+		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
+		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7794_pinmux_info = {
+	.name = "r8a7794_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_AD_CLK_B,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7794_pinmux_init(void)
+{
+	register_pinmux(&r8a7794_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index a64bfa18e0..6c706393d3 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,8 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
 
 ifndef CONFIG_SPL_BUILD
@@ -18,6 +20,8 @@ obj-y	+= cpu_info.o
 endif
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SUN4I)	+= dram.o
+obj-$(CONFIG_SUN5I)	+= dram.o
 obj-$(CONFIG_SUN7I)	+= dram.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 49c94489ee..8f2cef332f 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -11,6 +11,7 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <serial.h>
@@ -24,6 +25,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/timer.h>
 
+#include <linux/compiler.h>
+
 #ifdef CONFIG_SPL_BUILD
 /* Pointer to the global data structure for SPL */
 DECLARE_GLOBAL_DATA_PTR;
@@ -47,15 +50,38 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
+#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+	sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
 
 	return 0;
 }
 
 void reset_cpu(ulong addr)
 {
+	static const struct sunxi_wdog *wdog =
+		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+	/* Set the watchdog for its shortest interval (.5s) and wait */
+	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+
+	while (1) {
+		/* sun5i sometimes gets stuck without this */
+		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+	}
 }
 
 /* do some early init */
@@ -72,11 +98,16 @@ void s_init(void)
 	clock_init();
 	timer_init();
 	gpio_init();
+	i2c_init_board();
 
 #ifdef CONFIG_SPL_BUILD
 	gd = &gdata;
 	preloader_console_init();
 
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	/* Needed early by sunxi_board_init if PMU is enabled */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 	sunxi_board_init();
 #endif
 }
@@ -96,7 +127,15 @@ void enable_caches(void)
  */
 int cpu_eth_init(bd_t *bis)
 {
-	int rc;
+	__maybe_unused int rc;
+
+#ifdef CONFIG_SUNXI_EMAC
+	rc = sunxi_emac_initialize(bis);
+	if (rc < 0) {
+		printf("sunxi: failed to initialize emac\n");
+		return rc;
+	}
+#endif
 
 #ifdef CONFIG_SUNXI_GMAC
 	rc = sunxi_gmac_initialize(bis);
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 5a7da3c6bf..b8b16cff95 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -36,8 +36,7 @@ void clock_init_safe(void)
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
 #ifdef CONFIG_SUN7I
-	writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
-	       &ccm->ahb_gate0);
+	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b4c3d5c6dd..5cf35acc1e 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -13,7 +13,22 @@
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
+#ifdef CONFIG_SUN4I
+	puts("CPU:   Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN5I
+	u32 val = readl(SUNXI_SID_BASE + 0x08);
+	switch ((val >> 12) & 0xf) {
+	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
+	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
+	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
+	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
+	}
+#elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+	puts("CPU:   SUNXI Family\n");
+#endif
 	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index b43c4b41d3..0f1ceecc1d 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void)
 	struct sunxi_dram_reg *dram =
 			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
-	clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
-	udelay(2);
-	setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#ifdef CONFIG_SUN4I
+	struct sunxi_timer_reg *timer =
+			(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+	u32 reg_val;
+
+	writel(0, &timer->cpu_cfg);
+	reg_val = readl(&timer->cpu_cfg);
+
+	if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+	    CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+		udelay(2);
+		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+	} else
+#endif
+	{
+		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+		udelay(2);
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+	}
 }
 
 static void mctl_set_drive(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 
+#ifdef CONFIG_SUN7I
 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
 			DRAM_MCR_MODE_EN(0x3) |
 			0xffc);
 }
@@ -134,6 +155,26 @@ static void mctl_enable_dllx(u32 phase)
 }
 
 static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x1035,
+	0x1035, 0x0731, 0x1031, 0,
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0x0301, 0
+#endif
+#ifdef CONFIG_SUN4I
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0, 0,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x5031,
+	0x1035, 0x0731, 0x1031, 0x0735,
+	0x1035, 0x1031, 0x0731, 0x1035,
+	0x1031, 0x0301, 0x0301, 0x0731
+#endif
 #ifdef CONFIG_SUN7I
 	0x0301, 0x0301, 0x0301, 0x0301,
 	0x0301, 0x0301, 0x0301, 0x0301,
@@ -223,22 +264,38 @@ static void mctl_setup_dram_clock(u32 clk)
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
 #endif
 
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	/* setup MBUS clock */
 	reg_val = CCM_MBUS_CTRL_GATE |
+#ifdef CONFIG_SUN7I
 		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
 		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
 		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#else /* defined(CONFIG_SUN5I) */
+		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#endif
 	writel(reg_val, &ccm->mbus_clk_cfg);
+#endif
 
 	/*
 	 * open DRAMC AHB & DLL register clock
 	 * close it first
 	 */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
 	udelay(22);
 
 	/* then open it */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
 	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
 	udelay(22);
 }
 
@@ -385,6 +442,13 @@ static void dramc_clock_output_en(u32 on)
 	else
 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
 #endif
+#ifdef CONFIG_SUN4I
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	if (on)
+		setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+	else
+		clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
 }
 
 static const u16 tRFC_table[2][6] = {
@@ -420,12 +484,25 @@ unsigned long dramc_init(struct dram_para *para)
 	/* setup DRAM relative clock */
 	mctl_setup_dram_clock(para->clock);
 
+#ifdef CONFIG_SUN5I
+	/* Disable any pad power save control */
+	writel(0, &dram->ppwrsctl);
+#endif
+
 	/* reset external DRAM */
+#ifndef CONFIG_SUN7I
+	mctl_ddr3_reset();
+#endif
 	mctl_set_drive();
 
 	/* dram clock off */
 	dramc_clock_output_en(0);
 
+#ifdef CONFIG_SUN4I
+	/* select dram controller 1 */
+	writel(DRAM_CSEL_MAGIC, &dram->csel);
+#endif
+
 	mctl_itm_disable();
 	mctl_enable_dll0(para->tpr3);
 
@@ -482,6 +559,9 @@ unsigned long dramc_init(struct dram_para *para)
 		mctl_ddr3_reset();
 	else
 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#else
+	/* dram clock on */
+	dramc_clock_output_en(1);
 #endif
 
 	udelay(1);
@@ -490,6 +570,22 @@ unsigned long dramc_init(struct dram_para *para)
 
 	mctl_enable_dllx(para->tpr3);
 
+#ifdef CONFIG_SUN4I
+	/* set odt impedance divide ratio */
+	reg_val = ((para->zq) >> 8) & 0xfffff;
+	reg_val |= ((para->zq) & 0xff) << 20;
+	reg_val |= (para->zq) & 0xf0000000;
+	writel(reg_val, &dram->zqcr0);
+#endif
+
+#ifdef CONFIG_SUN4I
+	/* set I/O configure register */
+	reg_val = 0x00cc0000;
+	reg_val |= (para->odt_en) & 0x3;
+	reg_val |= ((para->odt_en) & 0x3) << 30;
+	writel(reg_val, &dram->iocr);
+#endif
+
 	/* set refresh period */
 	dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
 
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
index 364e35c32f..928b7c19e0 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
@@ -27,6 +27,11 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
 	. = .;
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
index 5008028aae..53f0cbd2b7 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -27,6 +27,7 @@ SECTIONS
 	.text      :
 	{
 		__start = .;
+		*(.vectors)
 		arch/arm/cpu/armv7/start.o	(.text)
 		*(.text*)
 	} > .sram
@@ -38,6 +39,11 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .sram
+
+	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
 
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
new file mode 100644
index 0000000000..0b0d6a76fc
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <asm/global_data.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+static int fdt_psci(void *fdt)
+{
+#ifdef CONFIG_ARMV7_PSCI
+	int nodeoff;
+	int tmp;
+
+	nodeoff = fdt_path_offset(fdt, "/cpus");
+	if (nodeoff < 0) {
+		printf("couldn't find /cpus\n");
+		return nodeoff;
+	}
+
+	/* add 'enable-method = "psci"' to each cpu node */
+	for (tmp = fdt_first_subnode(fdt, nodeoff);
+	     tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp)) {
+		const struct fdt_property *prop;
+		int len;
+
+		prop = fdt_get_property(fdt, tmp, "device_type", &len);
+		if (!prop)
+			continue;
+		if (len < 4)
+			continue;
+		if (strcmp(prop->data, "cpu"))
+			continue;
+
+		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
+	}
+
+	nodeoff = fdt_path_offset(fdt, "/psci");
+	if (nodeoff < 0) {
+		nodeoff = fdt_path_offset(fdt, "/");
+		if (nodeoff < 0)
+			return nodeoff;
+
+		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
+		if (nodeoff < 0)
+			return nodeoff;
+	}
+
+	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
+	if (tmp)
+		return tmp;
+#endif
+	return 0;
+}
+
+int armv7_update_dt(void *fdt)
+{
+#ifndef CONFIG_ARMV7_SECURE_BASE
+	/* secure code lives in RAM, keep it alive */
+	fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+			__secure_end - __secure_start);
+#endif
+
+	return fdt_psci(fdt);
+}
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f97f..651ca4015d 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -13,17 +13,10 @@
 #include <asm/armv7.h>
 #include <asm/gic.h>
 #include <asm/io.h>
+#include <asm/secure.h>
 
 unsigned long gic_dist_addr;
 
-static unsigned int read_cpsr(void)
-{
-	unsigned int reg;
-
-	asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
-	return reg;
-}
-
 static unsigned int read_id_pfr1(void)
 {
 	unsigned int reg;
@@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void)
 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
 	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
 #else
-	unsigned midr;
 	unsigned periphbase;
 
-	/* check whether we are an Cortex-A15 or A7.
-	 * The actual HYP switch should work with all CPUs supporting
-	 * the virtualization extension, but we need the GIC address,
-	 * which we know only for sure for those two CPUs.
-	 */
-	asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
-	switch (midr & MIDR_PRIMARY_PART_MASK) {
-	case MIDR_CORTEX_A9_R0P1:
-	case MIDR_CORTEX_A15_R0P0:
-	case MIDR_CORTEX_A7_R0P0:
-		break;
-	default:
-		printf("nonsec: could not determine GIC address.\n");
-		return -1;
-	}
-
 	/* get the GIC base address from the CBAR register */
 	asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
 
@@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void)
 #endif
 }
 
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV7_SECURE_BASE
+	size_t sz = __secure_end - __secure_start;
+
+	memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
+	flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
+			   CONFIG_ARMV7_SECURE_BASE + sz + 1);
+	invalidate_icache_all();
+#endif
+}
+
 static void kick_secondary_cpus_gic(unsigned long gicdaddr)
 {
 	/* kick all CPUs (except this one) by writing to GICD_SGIR */
@@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void)
 	kick_secondary_cpus_gic(gic_dist_addr);
 }
 
-int armv7_switch_hyp(void)
-{
-	unsigned int reg;
-
-	/* check whether we are in HYP mode already */
-	if ((read_cpsr() & 0x1f) == 0x1a) {
-		debug("CPU already in HYP mode\n");
-		return 0;
-	}
-
-	/* check whether the CPU supports the virtualization extensions */
-	reg = read_id_pfr1();
-	if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
-		printf("HYP mode: Virtualization extensions not implemented.\n");
-		return -1;
-	}
-
-	/* call the HYP switching code on this CPU also */
-	_switch_to_hyp();
-
-	if ((read_cpsr() & 0x1F) != 0x1a) {
-		printf("HYP mode: switch not successful.\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-int armv7_switch_nonsec(void)
+int armv7_init_nonsec(void)
 {
 	unsigned int reg;
 	unsigned itlinesnr, i;
@@ -147,11 +107,13 @@ int armv7_switch_nonsec(void)
 	for (i = 1; i <= itlinesnr; i++)
 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
 
-	smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+#ifndef CONFIG_ARMV7_PSCI
+	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
 	smp_kick_all_cpus();
+#endif
 
 	/* call the non-sec switching code on this CPU also */
-	_nonsec_init();
-
+	relocate_secure_section();
+	secure_ram_addr(_nonsec_init)();
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index e0ed3bfb43..1ea086d520 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
 	/* ECC is enabled when memory is in 16bit mode and it is enabled */
 	if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
 	    (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
-		puts("Memory: ECC enabled\n");
+		puts("ECC enabled ");
 		/*
 		 * Clear the first 1MB because it is not initialized from
 		 * first stage bootloader. To get ECC to work all memory has
@@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
 		 */
 		memset((void *)0, 0, 1 * 1024 * 1024);
 	} else {
-		puts("Memory: ECC disabled\n");
+		puts("ECC disabled ");
 	}
 }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index a7728e0a2d..7336162d80 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -7,6 +7,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
@@ -23,6 +25,34 @@ SECTIONS
 		*(.text*)
 	}
 
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
+
+#ifndef CONFIG_ARMV7_SECURE_BASE
+#define CONFIG_ARMV7_SECURE_BASE
+#endif
+
+	.__secure_start : {
+		. = ALIGN(0x1000);
+		*(.__secure_start)
+	}
+
+	.secure_text CONFIG_ARMV7_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	. = LOADADDR(.__secure_start) +
+		SIZEOF(.__secure_start) +
+		SIZEOF(.secure_text);
+
+	__secure_end_lma = .;
+	.__secure_end : AT(__secure_end_lma) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */
+	}
+#endif
+
 	. = ALIGN(4);
 	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 4d899528f5..97bbfe2e65 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -33,11 +33,7 @@
 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
 #define MT47H128M16RT25E_RATIO			0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT		0x00
 #define MT47H128M16RT25E_RD_DQS			0x12
-#define MT47H128M16RT25E_WR_DQS			0x00
-#define MT47H128M16RT25E_PHY_WRLVL		0x00
-#define MT47H128M16RT25E_PHY_GATELVL		0x00
 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index e7e8c58b00..b2412b56e1 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -59,13 +59,6 @@
 /* max number of GPMC regs */
 #define GPMC_MAX_REG		7
 
-#define PISMO1_NOR		1
-#define PISMO1_NAND		2
-#define PISMO2_CS0		3
-#define PISMO2_CS1		4
-#define PISMO1_ONENAND		5
 #define DBG_MPDB		6
-#define PISMO2_NAND_CS0		7
-#define PISMO2_NAND_CS1		8
 
 #endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
new file mode 100644
index 0000000000..41478110e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -0,0 +1,68 @@
+/*
+ * K2E: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2E_H
+#define __ASM_ARCH_CLOCK_K2E_H
+
+enum ext_clk_e {
+	sys_clk,
+	alt_core_clk,
+	pa_clk,
+	ddr3_clk,
+	mcm_clk,
+	pcie_clk,
+	sgmii_clk,
+	xgmii_clk,
+	usb_clk,
+	ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+	core_pll_clk,
+	pass_pll_clk,
+	ddr3_pll_clk,
+	sys_clk0_clk,
+	sys_clk0_1_clk,
+	sys_clk0_2_clk,
+	sys_clk0_3_clk,
+	sys_clk0_4_clk,
+	sys_clk0_6_clk,
+	sys_clk0_8_clk,
+	sys_clk0_12_clk,
+	sys_clk0_24_clk,
+	sys_clk1_clk,
+	sys_clk1_3_clk,
+	sys_clk1_4_clk,
+	sys_clk1_6_clk,
+	sys_clk1_12_clk,
+	sys_clk2_clk,
+	sys_clk3_clk
+};
+
+#define KS2_CLK1_6	sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+	CORE_PLL,
+	PASS_PLL,
+	DDR3_PLL,
+};
+
+#define CORE_PLL_800	{CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000	{CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200	{CORE_PLL, 24, 1, 2}
+#define PASS_PLL_1000	{PASS_PLL, 20, 1, 2}
+#define DDR3_PLL_200	{DDR3_PLL, 4,  1, 2}
+#define DDR3_PLL_400	{DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index 6a69a8d2be..784a0be567 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -10,10 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-#include <asm/arch/hardware.h>
-
-#ifndef __ASSEMBLY__
-
 enum ext_clk_e {
 	sys_clk,
 	alt_core_clk,
@@ -56,7 +52,7 @@ enum clk_e {
 	sys_clk3_clk
 };
 
-#define K2HK_CLK1_6 sys_clk0_6_clk
+#define KS2_CLK1_6 sys_clk0_6_clk
 
 /* PLL identifiers */
 enum pll_type_e {
@@ -66,15 +62,6 @@ enum pll_type_e {
 	DDR3A_PLL,
 	DDR3B_PLL,
 };
-#define MAIN_PLL CORE_PLL
-
-/* PLL configuration data */
-struct pll_init_data {
-	int pll;
-	int pll_m;		/* PLL Multiplier */
-	int pll_d;		/* PLL divider */
-	int pll_od;		/* PLL output divider    */
-};
 
 #define CORE_PLL_799    {CORE_PLL,	13,	1,	2}
 #define CORE_PLL_983    {CORE_PLL,	16,	1,	2}
@@ -98,12 +85,4 @@ struct pll_init_data {
 #define DDR3_PLL_800(x)	{DDR3##x##_PLL,	16,	1,	2}
 #define DDR3_PLL_333(x)	{DDR3##x##_PLL,	20,	1,	6}
 
-void init_plls(int num_pll, struct pll_init_data *config);
-void init_pll(const struct pll_init_data *data);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index 324501b75a..1513c76b6a 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -10,8 +10,40 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#ifndef __ASSEMBLY__
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/clock-k2hk.h>
 #endif
 
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/clock-k2e.h>
+#endif
+
+#define MAIN_PLL CORE_PLL
+
+#include <asm/types.h>
+
+struct keystone_pll_regs {
+	u32 reg0;
+	u32 reg1;
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+	int pll;
+	int pll_m;		/* PLL Multiplier */
+	int pll_d;		/* PLL divider */
+	int pll_od;		/* PLL output divider */
+};
+
+extern const struct keystone_pll_regs keystone_pll_regs[];
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
index b251aff383..e545341ca7 100644
--- a/arch/arm/include/asm/arch-keystone/clock_defs.h
+++ b/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -50,7 +50,7 @@ struct pllctl_regs {
 };
 
 static struct pllctl_regs *pllctl_regs[] = {
-	(struct pllctl_regs *)(CLOCK_BASE + 0x100)
+	(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
 };
 
 #define pllctl_reg(pll, reg)            (&(pllctl_regs[pll]->reg))
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
new file mode 100644
index 0000000000..4d229a25fa
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -0,0 +1,56 @@
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include <asm/arch/hardware.h>
+
+struct ddr3_phy_config {
+	unsigned int pllcr;
+	unsigned int pgcr1_mask;
+	unsigned int pgcr1_val;
+	unsigned int ptr0;
+	unsigned int ptr1;
+	unsigned int ptr2;
+	unsigned int ptr3;
+	unsigned int ptr4;
+	unsigned int dcr_mask;
+	unsigned int dcr_val;
+	unsigned int dtpr0;
+	unsigned int dtpr1;
+	unsigned int dtpr2;
+	unsigned int mr0;
+	unsigned int mr1;
+	unsigned int mr2;
+	unsigned int dtcr;
+	unsigned int pgcr2;
+	unsigned int zq0cr1;
+	unsigned int zq1cr1;
+	unsigned int zq2cr1;
+	unsigned int pir_v1;
+	unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+	unsigned int sdcfg;
+	unsigned int sdtim1;
+	unsigned int sdtim2;
+	unsigned int sdtim3;
+	unsigned int sdtim4;
+	unsigned int zqcfg;
+	unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_reset_ddrphy(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
new file mode 100644
index 0000000000..62172a4b84
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
@@ -0,0 +1,44 @@
+/*
+ * K2E: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2E_H
+#define __ASM_ARCH_HARDWARE_K2E_H
+
+/* PA SS Registers */
+#define KS2_PASS_BASE			0x24000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD_RST		0
+#define KS2_LPSC_USB_1			1
+#define KS2_LPSC_USB			2
+#define KS2_LPSC_EMIF25_SPI		3
+#define KS2_LPSC_TSIP			4
+#define KS2_LPSC_DEBUGSS_TRC		5
+#define KS2_LPSC_TETB_TRC		6
+#define KS2_LPSC_PKTPROC		7
+#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII			8
+#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO			9
+#define KS2_LPSC_PCIE			10
+#define KS2_LPSC_VUSR0			12
+#define KS2_LPSC_CHIP_SRSS		13
+#define KS2_LPSC_MSMC			14
+#define KS2_LPSC_EMIF4F_DDR3		23
+#define KS2_LPSC_PCIE_1			27
+#define KS2_LPSC_XGE			50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM	-1	/* not defined in K2E */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM	-1	/* not defined in K2E */
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS			1
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 50ce649d4c..eb132f73e6 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -6,136 +6,82 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
+
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define K2HK_PLL_CNTRL_BASE             0x02310000
-#define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
-#define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY                 0x5a69
-#define KS2_RSTCTRL_MASK                0xffff0000
-#define KS2_RSTCTRL_SWRST               0xfffe0000
-
-#define K2HK_PSC_BASE                   0x02350000
-#define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
-#define JTAG_ID_REG                     (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define K2HK_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-
-#define K2HK_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
-#define ARM_PLL_EN                      BIT(13)
+#define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
-#define K2HK_SPI0_BASE                  0x21000400
-#define K2HK_SPI1_BASE                  0x21000600
-#define K2HK_SPI2_BASE                  0x21000800
-#define K2HK_SPI_BASE                   K2HK_SPI0_BASE
-
-/* Chip configuration unlock codes and registers */
-#define KEYSTONE_KICK0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KEYSTONE_KICK1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KEYSTONE_KICK0_MAGIC           0x83e70b13
-#define KEYSTONE_KICK1_MAGIC           0x95a4f1e0
+#define KS2_ARM_PLL_EN			BIT(13)
 
 /* PA SS Registers */
-#define KS2_PASS_BASE                  0x02000000
+#define KS2_PASS_BASE			0x02000000
 
 /* PLL control registers */
-#define K2HK_MAINPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define K2HK_MAINPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define K2HK_PASSPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define K2HK_PASSPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define K2HK_DDR3APLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define K2HK_DDR3APLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
-#define K2HK_DDR3BPLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define K2HK_DDR3BPLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define K2HK_ARMPLLCTL0	               (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define K2HK_ARMPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 
 /* Power and Sleep Controller (PSC) Domains */
-#define K2HK_LPSC_MOD                  0
-#define K2HK_LPSC_DUMMY1               1
-#define K2HK_LPSC_USB                  2
-#define K2HK_LPSC_EMIF25_SPI           3
-#define K2HK_LPSC_TSIP                 4
-#define K2HK_LPSC_DEBUGSS_TRC          5
-#define K2HK_LPSC_TETB_TRC             6
-#define K2HK_LPSC_PKTPROC              7
-#define KS2_LPSC_PA                    K2HK_LPSC_PKTPROC
-#define K2HK_LPSC_SGMII                8
-#define KS2_LPSC_CPGMAC                K2HK_LPSC_SGMII
-#define K2HK_LPSC_CRYPTO               9
-#define K2HK_LPSC_PCIE                 10
-#define K2HK_LPSC_SRIO                 11
-#define K2HK_LPSC_VUSR0                12
-#define K2HK_LPSC_CHIP_SRSS            13
-#define K2HK_LPSC_MSMC                 14
-#define K2HK_LPSC_GEM_0                15
-#define K2HK_LPSC_GEM_1                16
-#define K2HK_LPSC_GEM_2                17
-#define K2HK_LPSC_GEM_3                18
-#define K2HK_LPSC_GEM_4                19
-#define K2HK_LPSC_GEM_5                20
-#define K2HK_LPSC_GEM_6                21
-#define K2HK_LPSC_GEM_7                22
-#define K2HK_LPSC_EMIF4F_DDR3A         23
-#define K2HK_LPSC_EMIF4F_DDR3B         24
-#define K2HK_LPSC_TAC                  25
-#define K2HK_LPSC_RAC                  26
-#define K2HK_LPSC_RAC_1                27
-#define K2HK_LPSC_FFTC_A               28
-#define K2HK_LPSC_FFTC_B               29
-#define K2HK_LPSC_FFTC_C               30
-#define K2HK_LPSC_FFTC_D               31
-#define K2HK_LPSC_FFTC_E               32
-#define K2HK_LPSC_FFTC_F               33
-#define K2HK_LPSC_AI2                  34
-#define K2HK_LPSC_TCP3D_0              35
-#define K2HK_LPSC_TCP3D_1              36
-#define K2HK_LPSC_TCP3D_2              37
-#define K2HK_LPSC_TCP3D_3              38
-#define K2HK_LPSC_VCP2X4_A             39
-#define K2HK_LPSC_CP2X4_B              40
-#define K2HK_LPSC_VCP2X4_C             41
-#define K2HK_LPSC_VCP2X4_D             42
-#define K2HK_LPSC_VCP2X4_E             43
-#define K2HK_LPSC_VCP2X4_F             44
-#define K2HK_LPSC_VCP2X4_G             45
-#define K2HK_LPSC_VCP2X4_H             46
-#define K2HK_LPSC_BCP                  47
-#define K2HK_LPSC_DXB                  48
-#define K2HK_LPSC_VUSR1                49
-#define K2HK_LPSC_XGE                  50
-#define K2HK_LPSC_ARM_SREFLEX          51
-#define K2HK_LPSC_TETRIS               52
+#define KS2_LPSC_MOD			0
+#define KS2_LPSC_DUMMY1			1
+#define KS2_LPSC_USB			2
+#define KS2_LPSC_EMIF25_SPI		3
+#define KS2_LPSC_TSIP			4
+#define KS2_LPSC_DEBUGSS_TRC		5
+#define KS2_LPSC_TETB_TRC		6
+#define KS2_LPSC_PKTPROC		7
+#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII			8
+#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO			9
+#define KS2_LPSC_PCIE			10
+#define KS2_LPSC_SRIO			11
+#define KS2_LPSC_VUSR0			12
+#define KS2_LPSC_CHIP_SRSS		13
+#define KS2_LPSC_MSMC			14
+#define KS2_LPSC_GEM_1			16
+#define KS2_LPSC_GEM_2			17
+#define KS2_LPSC_GEM_3			18
+#define KS2_LPSC_GEM_4			19
+#define KS2_LPSC_GEM_5			20
+#define KS2_LPSC_GEM_6			21
+#define KS2_LPSC_GEM_7			22
+#define KS2_LPSC_EMIF4F_DDR3A		23
+#define KS2_LPSC_EMIF4F_DDR3B		24
+#define KS2_LPSC_TAC			25
+#define KS2_LPSC_RAC			26
+#define KS2_LPSC_RAC_1			27
+#define KS2_LPSC_FFTC_A			28
+#define KS2_LPSC_FFTC_B			29
+#define KS2_LPSC_FFTC_C			30
+#define KS2_LPSC_FFTC_D			31
+#define KS2_LPSC_FFTC_E			32
+#define KS2_LPSC_FFTC_F			33
+#define KS2_LPSC_AI2			34
+#define KS2_LPSC_TCP3D_0		35
+#define KS2_LPSC_TCP3D_1		36
+#define KS2_LPSC_TCP3D_2		37
+#define KS2_LPSC_TCP3D_3		38
+#define KS2_LPSC_VCP2X4_A		39
+#define KS2_LPSC_CP2X4_B		40
+#define KS2_LPSC_VCP2X4_C		41
+#define KS2_LPSC_VCP2X4_D		42
+#define KS2_LPSC_VCP2X4_E		43
+#define KS2_LPSC_VCP2X4_F		44
+#define KS2_LPSC_VCP2X4_G		45
+#define KS2_LPSC_VCP2X4_H		46
+#define KS2_LPSC_BCP			47
+#define KS2_LPSC_DXB			48
+#define KS2_LPSC_VUSR1			49
+#define KS2_LPSC_XGE			50
+#define KS2_LPSC_ARM_SREFLEX		51
 
-/* DDR3A definitions */
-#define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
-#define K2HK_DDR3A_EMIF_DATA_BASE      0x80000000
-#define K2HK_DDR3A_DDRPHYC             0x02329000
 /* DDR3B definitions */
-#define K2HK_DDR3B_EMIF_CTRL_BASE      0x21020000
-#define K2HK_DDR3B_EMIF_DATA_BASE      0x60000000
-#define K2HK_DDR3B_DDRPHYC             0x02328000
-
-/* Queue manager */
-#define DEVICE_QM_MANAGER_BASE         0x02a02000
-#define DEVICE_QM_DESC_SETUP_BASE      0x02a03000
-#define DEVICE_QM_MANAGER_QUEUES_BASE  0x02a80000
-#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
-#define DEVICE_QM_QUEUE_STATUS_BASE    0x02a40000
-#define DEVICE_QM_NUM_LINKRAMS         2
-#define DEVICE_QM_NUM_MEMREGIONS       20
-
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE  0x02004000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE	0x02004800
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE	0x02005000
-
-#define DEVICE_PA_CDMA_RX_NUM_CHANNELS  24
-#define DEVICE_PA_CDMA_RX_NUM_FLOWS     32
-#define DEVICE_PA_CDMA_TX_NUM_CHANNELS  9
+#define KS2_DDR3B_EMIF_CTRL_BASE	0x21020000
+#define KS2_DDR3B_EMIF_DATA_BASE	0x60000000
+#define KS2_DDR3B_DDRPHYC		0x02328000
 
-/* MSMC control */
-#define K2HK_MSMC_CTRL_BASE             0x0bc00000
+/* Number of DSP cores */
+#define KS2_NUM_DSPS			8
 
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index ffdecbfcd6..ddeb06e7bb 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,42 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-struct ddr3_phy_config {
-	unsigned int pllcr;
-	unsigned int pgcr1_mask;
-	unsigned int pgcr1_val;
-	unsigned int ptr0;
-	unsigned int ptr1;
-	unsigned int ptr2;
-	unsigned int ptr3;
-	unsigned int ptr4;
-	unsigned int dcr_mask;
-	unsigned int dcr_val;
-	unsigned int dtpr0;
-	unsigned int dtpr1;
-	unsigned int dtpr2;
-	unsigned int mr0;
-	unsigned int mr1;
-	unsigned int mr2;
-	unsigned int dtcr;
-	unsigned int pgcr2;
-	unsigned int zq0cr1;
-	unsigned int zq1cr1;
-	unsigned int zq2cr1;
-	unsigned int pir_v1;
-	unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
-	unsigned int sdcfg;
-	unsigned int sdtim1;
-	unsigned int sdtim2;
-	unsigned int sdtim3;
-	unsigned int sdtim4;
-	unsigned int zqcfg;
-	unsigned int sdrfc;
-};
-
 #endif
 
 #define		BIT(x)	(1 << (x))
@@ -105,6 +69,11 @@ struct ddr3_emif_config {
 #define NOSRA_MASK                      0x08000000
 #define ECC_MASK                        0x00000001
 
+/* DDR3 definitions */
+#define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
+#define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
+#define KS2_DDR3A_DDRPHYC		0x02329000
+
 #define KS2_DDR3_MIDR_OFFSET            0x00
 #define KS2_DDR3_STATUS_OFFSET          0x04
 #define KS2_DDR3_SDCFG_OFFSET           0x08
@@ -116,39 +85,103 @@ struct ddr3_emif_config {
 #define KS2_DDR3_PMCTL_OFFSET           0x38
 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
 
+#define KS2_DDR3_PLLCTRL_PHY_RESET	0x80000000
+
 #define KS2_UART0_BASE                	0x02530c00
 #define KS2_UART1_BASE                	0x02531000
 
+/* Boot Config */
+#define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
+#define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+/* PSC */
+#define KS2_PSC_BASE			0x02350000
+#define KS2_LPSC_GEM_0			15
+#define KS2_LPSC_TETRIS			52
+#define KS2_TETRIS_PWR_DOMAIN		31
+
+/* Chip configuration unlock codes and registers */
+#define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KS2_KICK0_MAGIC			0x83e70b13
+#define KS2_KICK1_MAGIC			0x95a4f1e0
+
+/* PLL control registers */
+#define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+#define KS2_PLL_CNTRL_BASE		0x02310000
+#define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
+#define KS2_RSTCTRL_RSTYPE		(KS2_PLL_CNTRL_BASE + 0xe4)
+#define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY			0x5a69
+#define KS2_RSTCTRL_MASK		0xffff0000
+#define KS2_RSTCTRL_SWRST		0xfffe0000
+
+/* SPI */
+#define KS2_SPI0_BASE			0x21000400
+#define KS2_SPI1_BASE			0x21000600
+#define KS2_SPI2_BASE			0x21000800
+#define KS2_SPI_BASE			KS2_SPI0_BASE
+
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON		0x1
+
+/* Queue manager */
+#define KS2_QM_MANAGER_BASE		0x02a02000
+#define KS2_QM_DESC_SETUP_BASE		0x02a03000
+#define KS2_QM_MANAGER_QUEUES_BASEi	0x02a80000
+#define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
+#define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
+
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE		0x0bc00000
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
 
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/hardware-k2e.h>
+#endif
+
 #ifndef __ASSEMBLY__
 static inline int cpu_is_k2hk(void)
 {
-	unsigned int jtag_id	= __raw_readl(JTAG_ID_REG);
+	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
 	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
 
 	return (part_no == 0xb981) ? 1 : 0;
 }
 
+static inline int cpu_is_k2e(void)
+{
+	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
+	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
+
+	return (part_no == 0xb9a6) ? 1 : 0;
+}
+
 static inline int cpu_revision(void)
 {
-	unsigned int jtag_id	= __raw_readl(JTAG_ID_REG);
+	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
 	unsigned int rev	= (jtag_id >> 28) & 0xf;
 
 	return rev;
 }
 
-void share_all_segments(int priv_id);
 int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
 void sdelay(unsigned long);
 
 #endif
diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h
new file mode 100644
index 0000000000..33a28764bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/mon.h
@@ -0,0 +1,15 @@
+/*
+ * K2HK: secure kernel command header file
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _MON_H_
+#define _MON_H_
+
+int mon_power_off(int core_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
new file mode 100644
index 0000000000..c320db5b65
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -0,0 +1,17 @@
+/*
+ * MSMC controller
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _MSMC_H_
+#define _MSMC_H_
+
+#include <asm/arch/hardware.h>
+
+void msmc_share_all_segments(int priv_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index 7a688e46b0..f7bfa0e74d 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -129,7 +129,8 @@
  */
 #ifdef CONFIG_CMD_I2C
 #ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
 #endif
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 4d06ef83fe..53cc2b098a 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -98,7 +98,6 @@ struct ctrl_id {
 #define DEBUG_BASE		0x08000000	/* debug board */
 #define NAND_BASE		0x30000000	/* NAND addr */
 						/* (actual size small port) */
-#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
 #define ONENAND_MAP		0x20000000	/* OneNand addr */
 						/* (actual size small port) */
 /* SMS */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index d2dfb1e19a..0b78c1ca60 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -427,20 +427,7 @@ enum {
 /* max number of GPMC regs */
 #define GPMC_MAX_REG	7
 
-#define PISMO1_NOR	1
-#define PISMO1_NAND	2
-#define PISMO2_CS0	3
-#define PISMO2_CS1	4
-#define PISMO1_ONENAND	5
 #define DBG_MPDB	6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
-
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE		FLASH_BASE
-#define PISMO1_NAND_BASE	NAND_BASE
-#define PISMO2_CS0_BASE		PISMO2_MAP1
-#define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h
index 560e9f42d9..d25ea61e26 100644
--- a/arch/arm/include/asm/arch-rmobile/gpio.h
+++ b/arch/arm/include/asm/arch-rmobile/gpio.h
@@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
 #elif defined(CONFIG_R8A7791)
 #include "r8a7791-gpio.h"
 void r8a7791_pinmux_init(void);
+#elif defined(CONFIG_R8A7794)
+#include "r8a7794-gpio.h"
+void r8a7794_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
new file mode 100644
index 0000000000..a45a67c4d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
@@ -0,0 +1,176 @@
+#ifndef __ASM_R8A7794_H__
+#define __ASM_R8A7794_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+	GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+	GPIO_GP_6_24, GPIO_GP_6_25,
+
+	GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
+	GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
+	GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
+	GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
+	GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
+	GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
+	GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
+
+	/*
+	 * From IPSR0 to IPSR5 have been removed because they does not use.
+	 */
+
+	/* IPSR6 */
+	GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
+	GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
+	GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
+	GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
+	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
+	GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
+	GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
+	GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
+	GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
+	GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
+	GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
+	GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
+	GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
+	GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
+	GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
+	GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
+	GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
+
+	/* IPSR7 */
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
+	GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
+	GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
+	GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
+	GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
+	GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
+	GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
+	GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
+	GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
+	GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
+	GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
+	GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
+	GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
+	GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
+	GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
+	GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
+	GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
+	GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
+	GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
+	GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
+
+	/* IPSR8 */
+	GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
+	GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
+	GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
+	GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
+	GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
+	GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
+	GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
+	GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
+	GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
+	GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
+	GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
+	GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
+	GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
+	GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
+	GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
+	GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
+	GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
+	GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
+	GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
+	GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
+
+	/*
+	 * From IPSR9 to IPSR10 have been removed because they does not use.
+	 */
+
+	/* IPSR11 */
+	GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
+	GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
+	GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
+	GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
+	GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
+	GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
+	GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
+	GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+	GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
+	GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
+	GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
+	GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
+	GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
+	GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
+	GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
+	GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
+	GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
+	GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
+
+	/*
+	 * From IPSR12 to IPSR13 have been removed because they does not use.
+	 */
+};
+
+#endif /* __ASM_R8A7794_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
new file mode 100644
index 0000000000..94276ddc75
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7794.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_R8A7794_H
+#define __ASM_ARCH_R8A7794_H
+
+#include "rcar-base.h"
+
+#endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 41240f3320..027e9b1b14 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -10,7 +10,7 @@
 #define __ASM_ARCH_RCAR_BASE_H
 
 /*
- * R-Car (R8A7790/R8A7791) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
  */
 #define RWDT_BASE		0xE6020000
 #define SWDT_BASE		0xE6030000
@@ -116,7 +116,7 @@
 #define SYS_AXI_SAT1_BASE	0xFF8009C0
 #define SYS_AXI_SDM0_BASE	0xFF800A00
 #define SYS_AXI_SDM1_BASE	0xFF800A40
-#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_TRAB_BASE	0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
 #define SYS_AXI_UDM0_BASE	0xFF800B80
 #define SYS_AXI_UDM1_BASE	0xFF800BC0
 
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index ebddd7a8fe..2cc38e1b5b 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -10,6 +10,8 @@
 #include <asm/arch/r8a7790.h>
 #elif defined(CONFIG_R8A7791)
 #include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7794)
+#include <asm/arch/r8a7794.h>
 #else
 #error "SOC Name not defined"
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 892479c183..f7f3d8c41a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio(const char *name);
+#define name_to_gpio(name) sunxi_name_to_gpio(name)
 
 #endif /* _SUNXI_GPIO_H */
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
new file mode 100644
index 0000000000..dc5406b213
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SUNXI_I2C_H_
+#define _SUNXI_I2C_H_
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
+/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+#define CONFIG_SYS_TCLK		24000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 6aacfd7b39..58e14fd0f7 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -11,6 +11,11 @@
 #ifndef _SUNXI_TIMER_H_
 #define _SUNXI_TIMER_H_
 
+#define WDT_CTRL_RESTART	(0x1 << 0)
+#define WDT_CTRL_KEY		(0x0a57 << 1)
+#define WDT_MODE_EN		(0x1 << 0)
+#define WDT_MODE_RESET_EN	(0x1 << 1)
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 395444ee4f..323f282fb7 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -78,13 +78,18 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
 
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
 
-int armv7_switch_nonsec(void);
-int armv7_switch_hyp(void);
+int armv7_init_nonsec(void);
+int armv7_update_dt(void *fdt);
 
 /* defined in assembly file */
 unsigned int _nonsec_init(void);
+void _do_nonsec_entry(void *target_pc, unsigned long r0,
+		      unsigned long r1, unsigned long r2);
 void _smp_pen(void);
-void _switch_to_hyp(void);
+
+extern char __secure_start[];
+extern char __secure_end[];
+
 #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
 
 #endif /* ! __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d1344ee94c..183823404d 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -595,6 +595,14 @@ static inline u32 omap_revision(void)
 	return *omap_si_rev;
 }
 
+#define OMAP44xx	0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
 #define OMAP54xx	0x54000000
 
 static inline u8 is_omap54xx(void)
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
index 21aef58b7b..71df5a9e25 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -38,12 +38,14 @@ struct pt_regs {
 #define IRQ_MODE	0x12
 #define SVC_MODE	0x13
 #define ABT_MODE	0x17
+#define HYP_MODE	0x1a
 #define UND_MODE	0x1b
 #define SYSTEM_MODE	0x1f
 #define MODE_MASK	0x1f
 #define T_BIT		0x20
 #define F_BIT		0x40
 #define I_BIT		0x80
+#define A_BIT		0x100
 #define CC_V_BIT	(1 << 28)
 #define CC_C_BIT	(1 << 29)
 #define CC_Z_BIT	(1 << 30)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
new file mode 100644
index 0000000000..704b4b0018
--- /dev/null
+++ b/arch/arm/include/asm/psci.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_PSCI_H__
+#define __ARM_PSCI_H__
+
+/* PSCI interface */
+#define ARM_PSCI_FN_BASE		0x95c1ba5e
+#define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
+
+#define ARM_PSCI_FN_CPU_SUSPEND		ARM_PSCI_FN(0)
+#define ARM_PSCI_FN_CPU_OFF		ARM_PSCI_FN(1)
+#define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
+#define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
+
+#define ARM_PSCI_RET_SUCCESS		0
+#define ARM_PSCI_RET_NI			(-1)
+#define ARM_PSCI_RET_INVAL		(-2)
+#define ARM_PSCI_RET_DENIED		(-3)
+
+#endif /* __ARM_PSCI_H__ */
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
new file mode 100644
index 0000000000..effdb1858d
--- /dev/null
+++ b/arch/arm/include/asm/secure.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_SECURE_H
+#define __ASM_SECURE_H
+
+#include <config.h>
+
+#ifdef CONFIG_ARMV7_SECURE_BASE
+/*
+ * Warning, horror ahead.
+ *
+ * The target code lives in our "secure ram", but u-boot doesn't know
+ * that, and has blindly added reloc_off to every relocation
+ * entry. Gahh. Do the opposite conversion. This hack also prevents
+ * GCC from generating code veeners, which u-boot doesn't relocate at
+ * all...
+ */
+#define secure_ram_addr(_fn) ({						\
+			DECLARE_GLOBAL_DATA_PTR;			\
+			void *__fn = _fn;				\
+			typeof(_fn) *__tmp = (__fn - gd->reloc_off);	\
+			__tmp;						\
+		})
+#else
+#define secure_ram_addr(_fn)	(_fn)
+#endif
+
+#endif
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index e40691d15f..d4f1578e9e 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -17,13 +17,14 @@
 
 #include <common.h>
 #include <fdt_support.h>
+#include <asm/armv7.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int arch_fixup_memory_node(void *blob)
+int arch_fixup_fdt(void *blob)
 {
 	bd_t *bd = gd->bd;
-	int bank;
+	int bank, ret;
 	u64 start[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -32,5 +33,12 @@ int arch_fixup_memory_node(void *blob)
 		size[bank] = bd->bi_dram[bank].size;
 	}
 
-	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+	if (ret)
+		return ret;
+
+	ret = armv7_update_dt(blob);
+#endif
+	return ret;
 }
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 47ee070593..178e8fb9e4 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -20,6 +20,7 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
+#include <asm/secure.h>
 #include <linux/compiler.h>
 
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
@@ -184,27 +185,17 @@ static void setup_end_tag(bd_t *bd)
 
 __weak void setup_board_tags(struct tag **in_params) {}
 
+#ifdef CONFIG_ARM64
 static void do_nonsec_virt_switch(void)
 {
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
-	if (armv7_switch_nonsec() == 0)
-#ifdef CONFIG_ARMV7_VIRT
-		if (armv7_switch_hyp() == 0)
-			debug("entered HYP mode\n");
-#else
-		debug("entered non-secure state\n");
-#endif
-#endif
-
-#ifdef CONFIG_ARM64
 	smp_kick_all_cpus();
 	flush_dcache_all();	/* flush cache before swtiching to EL2 */
 	armv8_switch_to_el2();
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
 	armv8_switch_to_el1();
 #endif
-#endif
 }
+#endif
 
 /* Subcommand: PREP */
 static void boot_prep_linux(bootm_headers_t *images)
@@ -242,7 +233,6 @@ static void boot_prep_linux(bootm_headers_t *images)
 		printf("FDT and ATAGS support not compiled in - hanging\n");
 		hang();
 	}
-	do_nonsec_virt_switch();
 }
 
 /* Subcommand: GO */
@@ -260,8 +250,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
 	announce_and_cleanup(fake);
 
-	if (!fake)
+	if (!fake) {
+		do_nonsec_virt_switch();
 		kernel_entry(images->ft_addr);
+	}
 #else
 	unsigned long machid = gd->bd->bi_arch_number;
 	char *s;
@@ -287,9 +279,16 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 	else
 		r2 = gd->bd->bi_boot_params;
 
-	if (!fake)
+	if (!fake) {
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+		armv7_init_nonsec();
+		secure_ram_addr(_do_nonsec_entry)(kernel_entry,
+						  0, machid, r2);
+#else
 		kernel_entry(0, machid, r2);
 #endif
+	}
+#endif
 }
 
 /* Main Entry point for arm bootm implementation
@@ -360,7 +359,7 @@ void boot_prep_vxworks(bootm_headers_t *images)
 	if (images->ft_addr) {
 		off = fdt_path_offset(images->ft_addr, "/memory");
 		if (off < 0) {
-			if (arch_fixup_memory_node(images->ft_addr))
+			if (arch_fixup_fdt(images->ft_addr))
 				puts("## WARNING: fixup memory failed!\n");
 		}
 	}
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 758b01371e..f6b7c03578 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -103,7 +103,7 @@ void show_regs (struct pt_regs *regs)
 	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
 	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
 	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK8_32",	"UK9_32",	"HYP_32",	"UND_32",
 	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
 	};
 
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 5b30bcb9a5..a1205c370d 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -25,4 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
 char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
 char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
 char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __secure_start[0] __attribute__((section(".__secure_start")));
+char __secure_end[0] __attribute__((section(".__secure_end")));
 char _end[0] __attribute__((section(".__end")));
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
index 7cddb85a7f..b8be3182a0 100644
--- a/arch/blackfin/cpu/jtag-console.c
+++ b/arch/blackfin/cpu/jtag-console.c
@@ -112,11 +112,11 @@ static void jtag_send(const char *raw_str, uint32_t len)
 	if (cooked_str != raw_str)
 		free((char *)cooked_str);
 }
-static void jtag_putc(const char c)
+static void jtag_putc(struct stdio_dev *dev, const char c)
 {
 	jtag_send(&c, 1);
 }
-static void jtag_puts(const char *s)
+static void jtag_puts(struct stdio_dev *dev, const char *s)
 {
 	jtag_send(s, strlen(s));
 }
@@ -133,7 +133,7 @@ static int jtag_tstc_dbg(void)
 }
 
 /* Higher layers want to know when any data is available */
-static int jtag_tstc(void)
+static int jtag_tstc(struct stdio_dev *dev)
 {
 	return jtag_tstc_dbg() || leftovers_len;
 }
@@ -142,7 +142,7 @@ static int jtag_tstc(void)
  * [32bit length][actual data]
  */
 static uint32_t leftovers;
-static int jtag_getc(void)
+static int jtag_getc(struct stdio_dev *dev)
 {
 	int ret;
 	uint32_t emudat;
@@ -173,7 +173,7 @@ static int jtag_getc(void)
 		leftovers = emudat;
 	}
 
-	return jtag_getc();
+	return jtag_getc(dev);
 }
 
 int drv_jtag_console_init(void)
diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h
index b97d267423..4fbc0405f7 100644
--- a/arch/m68k/include/asm/posix_types.h
+++ b/arch/m68k/include/asm/posix_types.h
@@ -15,7 +15,7 @@ typedef long		__kernel_off_t;
 typedef int		__kernel_pid_t;
 typedef unsigned int	__kernel_uid_t;
 typedef unsigned int	__kernel_gid_t;
-typedef unsigned long	__kernel_size_t;
+typedef unsigned int	__kernel_size_t;
 typedef int		__kernel_ssize_t;
 typedef long		__kernel_ptrdiff_t;
 typedef long		__kernel_time_t;
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index 42e0dc96f7..4105a28509 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -384,7 +384,7 @@ struct stdio_dev *open_port(int num, int baudrate)
 		sprintf(env_val, "%d", baudrate);
 		setenv(env_var, env_val);
 
-		if (port->start())
+		if (port->start(port))
 			return NULL;
 
 		set_bit(num, &initialized);
@@ -407,7 +407,7 @@ int close_port(int num)
 	if (!port)
 		return -1;
 
-	ret = port->stop();
+	ret = port->stop(port);
 	clear_bit(num, &initialized);
 
 	return ret;
@@ -418,7 +418,7 @@ int write_port(struct stdio_dev *port, char *buf)
 	if (!port || !buf)
 		return -1;
 
-	port->puts(buf);
+	port->puts(port, buf);
 
 	return 0;
 }
@@ -433,8 +433,8 @@ int read_port(struct stdio_dev *port, char *buf, int size)
 	if (!size)
 		return 0;
 
-	while (port->tstc()) {
-		buf[cnt++] = port->getc();
+	while (port->tstc(port)) {
+		buf[cnt++] = port->getc(port);
 		if (cnt > size)
 			break;
 	}
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 2fd5b11fe4..9590bfd3fd 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -948,7 +948,7 @@ static inline void console_newline (void)
 	}
 }
 
-void video_putc (const char c)
+void video_putc(struct stdio_dev *dev, const char c)
 {
 	if (!video_enable) {
 		serial_putc (c);
@@ -985,7 +985,7 @@ void video_putc (const char c)
 	}
 }
 
-void video_puts (const char *s)
+void video_puts(struct stdio_dev *dev, const char *s)
 {
 	int count = strlen (s);
 
@@ -994,7 +994,7 @@ void video_puts (const char *s)
 			serial_putc (*s++);
 	else
 		while (count--)
-			video_putc (*s++);
+			video_putc(dev, *s++);
 }
 
 /************************************************************************/
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 3f4005b5d7..1aa397c5e7 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <dm/root.h>
 #include <os.h>
 #include <asm/state.h>
 
@@ -14,6 +15,9 @@ void reset_cpu(ulong ignored)
 	if (state_uninit())
 		os_exit(2);
 
+	if (dm_uninit())
+		os_exit(2);
+
 	/* This is considered normal termination for now */
 	os_exit(0);
 }
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index aad3b8b147..b3d70515dc 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <os.h>
 #include <asm/getopt.h>
+#include <asm/io.h>
 #include <asm/sections.h>
 #include <asm/state.h>
 
@@ -218,6 +219,7 @@ SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1,
 int main(int argc, char *argv[])
 {
 	struct sandbox_state *state;
+	gd_t data;
 	int ret;
 
 	ret = state_init();
@@ -236,6 +238,12 @@ int main(int argc, char *argv[])
 	if (state->ram_buf_rm && state->ram_buf_fname)
 		os_unlink(state->ram_buf_fname);
 
+	memset(&data, '\0', sizeof(data));
+	gd = &data;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
+
 	/* Do pre- and post-relocation init */
 	board_init_f(0);
 
diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h
index 6c1bff99c2..ec7729eb4c 100644
--- a/arch/sandbox/include/asm/config.h
+++ b/arch/sandbox/include/asm/config.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
 #define CONFIG_SANDBOX_ARCH
 
 /* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds
deleted file mode 100644
index 254d9f274b..0000000000
--- a/arch/sh/cpu/sh2/u-boot.lds
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
-	/*
-	 * entry and reloct_dst will be provided via ldflags
-	 */
-	. = .;
-
-	PROVIDE (_ftext = .);
-	PROVIDE (_fcode = .);
-	PROVIDE (_start = .);
-
-	.text :
-	{
-		KEEP(arch/sh/cpu/sh2/start.o	(.text))
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenv)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenvr)
-		. = ALIGN(8192);
-		*(.text)
-		. = ALIGN(4);
-	} =0xFF
-	PROVIDE (_ecode = .);
-	.rodata :
-	{
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	}
-	PROVIDE (_etext = .);
-
-
-	PROVIDE (_fdata = .);
-	.data :
-	{
-		*(.data)
-		. = ALIGN(4);
-	}
-	PROVIDE (_edata = .);
-
-	PROVIDE (_fgot = .);
-	.got :
-	{
-		*(.got)
-		. = ALIGN(4);
-	}
-	PROVIDE (_egot = .);
-
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	PROVIDE (reloc_dst_end = .);
-
-	PROVIDE (bss_start = .);
-	PROVIDE (__bss_start = .);
-	.bss :
-	{
-		*(.bss)
-		. = ALIGN(4);
-	}
-	PROVIDE (bss_end = .);
-
-	PROVIDE (__bss_end = .);
-}
diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds
deleted file mode 100644
index 57544ce040..0000000000
--- a/arch/sh/cpu/sh4/u-boot.lds
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2008-2009
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
-	/*
-	 * entry and reloct_dst will be provided via ldflags
-	 */
-	. = .;
-
-	PROVIDE (_ftext = .);
-	PROVIDE (_fcode = .);
-	PROVIDE (_start = .);
-
-	.text :
-	{
-		KEEP(arch/sh/cpu/sh4/start.o		(.text))
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenv)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenvr)
-		. = ALIGN(8192);
-		*(.text)
-		. = ALIGN(4);
-	} =0xFF
-	PROVIDE (_ecode = .);
-	.rodata :
-	{
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	}
-	PROVIDE (_etext = .);
-
-
-	PROVIDE (_fdata = .);
-	.data :
-	{
-		*(.data)
-		. = ALIGN(4);
-	}
-	PROVIDE (_edata = .);
-
-	PROVIDE (_fgot = .);
-	.got :
-	{
-		*(.got)
-		. = ALIGN(4);
-	}
-	PROVIDE (_egot = .);
-
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	PROVIDE (reloc_dst_end = .);
-	/* _reloc_dst_end = .; */
-
-	PROVIDE (bss_start = .);
-	PROVIDE (__bss_start = .);
-	.bss (NOLOAD) :
-	{
-		*(.bss)
-		. = ALIGN(4);
-	}
-	PROVIDE (bss_end = .);
-
-	PROVIDE (__bss_end = .);
-}
diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 26de08606a..30c7a9d3f8 100644
--- a/arch/sh/cpu/sh3/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -1,10 +1,10 @@
 /*
  * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2007
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
+ * Copyright (C) 2008-2009
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
  * Copyright (C) 2008
  * Mark Jonas <mark.jonas@de.bosch.com>
  *
@@ -28,7 +28,7 @@ SECTIONS
 
 	.text :
 	{
-		KEEP(arch/sh/cpu/sh3/start.o	(.text))
+		KEEP(*/start.o		(.text))
 		. = ALIGN(8192);
 		common/env_embedded.o	(.ppcenv)
 		. = ALIGN(8192);
diff --git a/board/gaisler/grsim/u-boot.lds b/arch/sparc/cpu/u-boot.lds
index cdc83941ed..1ade3b344b 100644
--- a/board/gaisler/grsim/u-boot.lds
+++ b/arch/sparc/cpu/u-boot.lds
@@ -1,7 +1,5 @@
 /*
- * Linker script for Gaisler Research AB's GRSIM LEON3 simulator.
- *
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -43,7 +41,7 @@ SECTIONS
 		_text = .;
 
 		*(.start)
-		arch/sparc/cpu/leon3/start.o (.text)
+		*/start.o (.text)
 /* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c
index dfd2a8496e..975949daa3 100644
--- a/arch/x86/lib/video.c
+++ b/arch/x86/lib/video.c
@@ -104,7 +104,7 @@ static void __video_putc(const char c, int *x, int *y)
 	}
 }
 
-static void video_putc(const char c)
+static void video_putc(struct stdio_dev *dev, const char c)
 {
 	int x, y, pos;
 
@@ -123,7 +123,7 @@ static void video_putc(const char c)
 	outb_p(0xff & (pos >> 1), vidport+1);
 }
 
-static void video_puts(const char *s)
+static void video_puts(struct stdio_dev *dev, const char *s)
 {
 	int x, y, pos;
 	char c;
@@ -178,8 +178,6 @@ int video_init(void)
 	vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
 	vga_dev.putc  = video_putc;        /* 'putc' function */
 	vga_dev.puts  = video_puts;        /* 'puts' function */
-	vga_dev.tstc  = NULL;              /* 'tstc' function */
-	vga_dev.getc  = NULL;              /* 'getc' function */
 
 	if (stdio_register(&vga_dev) == 0)
 		return 1;
@@ -191,8 +189,6 @@ int video_init(void)
 	strcpy(kbd_dev.name, "kbd");
 	kbd_dev.ext   = 0;
 	kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-	kbd_dev.putc  = NULL;        /* 'putc' function */
-	kbd_dev.puts  = NULL;        /* 'puts' function */
 	kbd_dev.tstc  = i8042_tstc;  /* 'tstc' function */
 	kbd_dev.getc  = i8042_getc;  /* 'getc' function */
 
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
index 5d8a0910de..c2bf145013 100644
--- a/board/bf527-ezkit/video.c
+++ b/board/bf527-ezkit/video.c
@@ -391,14 +391,6 @@ void video_stop(void)
 #endif
 }
 
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
 int drv_video_init(void)
 {
 	int error, devices = 1;
@@ -448,8 +440,6 @@ int drv_video_init(void)
 	strcpy(videodev.name, "video");
 	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
 	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
-	videodev.putc = video_putc;	/* 'putc' function */
-	videodev.puts = video_puts;	/* 'puts' function */
 
 	error = stdio_register(&videodev);
 
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
index 6737ac1628..47e68c6a97 100644
--- a/board/bf548-ezkit/video.c
+++ b/board/bf548-ezkit/video.c
@@ -281,14 +281,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
 
 }
 
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
 int drv_video_init(void)
 {
 	int error, devices = 1;
@@ -338,8 +330,6 @@ int drv_video_init(void)
 	strcpy(videodev.name, "video");
 	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
 	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
-	videodev.putc = video_putc;	/* 'putc' function */
-	videodev.puts = video_puts;	/* 'puts' function */
 
 	error = stdio_register(&videodev);
 
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index c35d285070..b098615d4c 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -283,14 +283,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
 
 }
 
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
 int drv_video_init(void)
 {
 	int error, devices = 1;
@@ -342,8 +334,6 @@ int drv_video_init(void)
 	strcpy(videodev.name, "video");
 	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
 	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
-	videodev.putc = video_putc;	/* 'putc' function */
-	videodev.puts = video_puts;	/* 'puts' function */
 
 	error = stdio_register(&videodev);
 
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index 803179a472..95d18911c3 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -12,9 +12,6 @@
 #endif
 
 #if defined(CONFIG_CMD_BSP)
-
-extern int do_source (cmd_tbl_t *, int, int, char *[]);
-
 #define ADDRMASK 0xfffff000
 
 /*
@@ -27,7 +24,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	int count2 = 0;
 	char addr[16];
 	char str[] = "\\|/-";
-	char *local_args[2];
 	u32 la, ptm1la;
 
 #if defined(CONFIG_440)
@@ -84,9 +80,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			 * Boot image via "source" command
 			 */
 			printf("executing script at addr 0x%s ...\n", addr);
-			local_args[0] = addr;
-			local_args[1] = NULL;
-			do_source(cmdtp, 0, 1, local_args);
+			source(la, NULL);
 			break;
 
 		case 2:
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 16bba59ba8..071701d234 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -56,14 +56,16 @@ ulong flash_init(void)
 
 int flash_get_offsets(ulong base, flash_info_t * info)
 {
-	int j, k;
+	int i;
 
 	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 
 		info->start[0] = base;
-		for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
-			info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
-			info->protect[k] = 0;
+		info->protect[0] = 0;
+		for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+			info->start[i] = info->start[i - 1]
+						+ CONFIG_SYS_SST_SECTSZ;
+			info->protect[i] = 0;
 		}
 	}
 
diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds
deleted file mode 100644
index 6d9c90cd71..0000000000
--- a/board/gaisler/gr_cpci_ax2000/u-boot.lds
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GR-CPCI-AX2000 board
- * with template design.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
-	. = + SIZEOF_HEADERS;
-	.interp : { *(.interp) }
-	.hash          : { *(.hash)		}
-	.dynsym        : { *(.dynsym)		}
-	.dynstr        : { *(.dynstr)		}
-	.rel.text      : { *(.rel.text)		}
-	.rela.text     : { *(.rela.text)	}
-	.rel.data      : { *(.rel.data)		}
-	.rela.data     : { *(.rela.data)	}
-	.rel.rodata    : { *(.rel.rodata)	}
-	.rela.rodata   : { *(.rela.rodata)	}
-	.rel.got       : { *(.rel.got)		}
-	.rela.got      : { *(.rela.got)		}
-	.rel.ctors     : { *(.rel.ctors)	}
-	.rela.ctors    : { *(.rela.ctors)	}
-	.rel.dtors     : { *(.rel.dtors)	}
-	.rela.dtors    : { *(.rela.dtors)	}
-	.rel.bss       : { *(.rel.bss)		}
-	.rela.bss      : { *(.rela.bss)		}
-	.rel.plt       : { *(.rel.plt)		}
-	.rela.plt      : { *(.rela.plt)		}
-	.init          : { *(.init)		}
-	.plt : { *(.plt) }
-
-	.text : {
-		_load_addr = .;
-		_text = .;
-
-		*(.start)
-		arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
-		. = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
-		__prom_start = .;
-		*(.prom.pgt)
-		*(.prom.data)
-		*(.prom.text)
-		. = ALIGN(16);
-		__prom_end = .;
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-/*		*(.got1)*/
-		. = ALIGN(16);
-		*(.eh_frame)
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	_etext = .;
-
-	/* CMD Table */
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	.data	:
-	{
-		*(.data)
-		*(.data1)
-		*(.data.rel)
-		*(.data.rel.*)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	}
-	_edata	=	.;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__got_start = .;
-	.got : {
-		*(.got)
-/*		*(.data.rel)
-		*(.data.rel.local)*/
-		. = ALIGN(16);
-	}
-	__got_end = .;
-
-/*	.data.rel : { } */
-
-	. = ALIGN(4096);
-	__init_begin = .;
-	.text.init : { *(.text.init) }
-	.data.init : { *(.data.init) }
-	. = ALIGN(4096);
-	__init_end = .;
-
-	__bss_start = .;
-	.bss		:
-	{
-	 *(.sbss) *(.scommon)
-	 *(.dynbss)
-	 *(.bss)
-	 *(COMMON)
-	. = ALIGN(16); /* to speed clearing of bss up */
-	}
-	__bss_end = . ;
-	__bss_end = . ;
-	PROVIDE (end = .);
-
-/* Relocated into main memory */
-
-	/* Start of main memory */
-	/*. = 0x40000000;*/
-
-	.stack (NOLOAD)	: { *(.stack) }
-
-	/* PROM CODE */
-
-	/* global data in RAM passed to kernel after booting */
-
-  .stab 0		: { *(.stab) }
-  .stabstr 0		: { *(.stabstr) }
-  .stab.excl 0		: { *(.stab.excl) }
-  .stab.exclstr 0	: { *(.stab.exclstr) }
-  .stab.index 0		: { *(.stab.index) }
-  .stab.indexstr 0	: { *(.stab.indexstr) }
-  .comment 0		: { *(.comment) }
-
-}
diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds
deleted file mode 100644
index 973603c7cc..0000000000
--- a/board/gaisler/gr_ep2s60/u-boot.lds
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's Template design
- * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
-	. = + SIZEOF_HEADERS;
-	.interp : { *(.interp) }
-	.hash          : { *(.hash)		}
-	.dynsym        : { *(.dynsym)		}
-	.dynstr        : { *(.dynstr)		}
-	.rel.text      : { *(.rel.text)		}
-	.rela.text     : { *(.rela.text)	}
-	.rel.data      : { *(.rel.data)		}
-	.rela.data     : { *(.rela.data)	}
-	.rel.rodata    : { *(.rel.rodata)	}
-	.rela.rodata   : { *(.rela.rodata)	}
-	.rel.got       : { *(.rel.got)		}
-	.rela.got      : { *(.rela.got)		}
-	.rel.ctors     : { *(.rel.ctors)	}
-	.rela.ctors    : { *(.rela.ctors)	}
-	.rel.dtors     : { *(.rel.dtors)	}
-	.rela.dtors    : { *(.rela.dtors)	}
-	.rel.bss       : { *(.rel.bss)		}
-	.rela.bss      : { *(.rela.bss)		}
-	.rel.plt       : { *(.rel.plt)		}
-	.rela.plt      : { *(.rela.plt)		}
-	.init          : { *(.init)		}
-	.plt : { *(.plt) }
-
-	.text : {
-		_load_addr = .;
-		_text = .;
-
-		*(.start)
-		arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
-		. = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
-		__prom_start = .;
-		*(.prom.pgt)
-		*(.prom.data)
-		*(.prom.text)
-		. = ALIGN(16);
-		__prom_end = .;
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-/*		*(.got1)*/
-		. = ALIGN(16);
-		*(.eh_frame)
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	_etext = .;
-
-	/* CMD Table */
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	.data	:
-	{
-		*(.data)
-		*(.data1)
-		*(.data.rel)
-		*(.data.rel.*)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	}
-	_edata	=	.;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__got_start = .;
-	.got : {
-		*(.got)
-/*		*(.data.rel)
-		*(.data.rel.local)*/
-		. = ALIGN(16);
-	}
-	__got_end = .;
-
-/*	.data.rel : { } */
-
-	. = ALIGN(4096);
-	__init_begin = .;
-	.text.init : { *(.text.init) }
-	.data.init : { *(.data.init) }
-	. = ALIGN(4096);
-	__init_end = .;
-
-	__bss_start = .;
-	.bss		:
-	{
-	 *(.sbss) *(.scommon)
-	 *(.dynbss)
-	 *(.bss)
-	 *(COMMON)
-	. = ALIGN(16); /* to speed clearing of bss up */
-	}
-	__bss_end = . ;
-	__bss_end = . ;
-	PROVIDE (end = .);
-
-/* Relocated into main memory */
-
-	/* Start of main memory */
-	/*. = 0x40000000;*/
-
-	.stack (NOLOAD)	: { *(.stack) }
-
-	/* PROM CODE */
-
-	/* global data in RAM passed to kernel after booting */
-
-  .stab 0		: { *(.stab) }
-  .stabstr 0		: { *(.stabstr) }
-  .stab.excl 0		: { *(.stab.excl) }
-  .stab.exclstr 0	: { *(.stab.exclstr) }
-  .stab.index 0		: { *(.stab.index) }
-  .stab.indexstr 0	: { *(.stab.indexstr) }
-  .comment 0		: { *(.comment) }
-
-}
diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds
deleted file mode 100644
index 1ed71f2659..0000000000
--- a/board/gaisler/gr_xc3s_1500/u-boot.lds
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GR-XC3S-1500 board
- * with template design.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
-	. = + SIZEOF_HEADERS;
-	.interp : { *(.interp) }
-	.hash          : { *(.hash)		}
-	.dynsym        : { *(.dynsym)		}
-	.dynstr        : { *(.dynstr)		}
-	.rel.text      : { *(.rel.text)		}
-	.rela.text     : { *(.rela.text)	}
-	.rel.data      : { *(.rel.data)		}
-	.rela.data     : { *(.rela.data)	}
-	.rel.rodata    : { *(.rel.rodata)	}
-	.rela.rodata   : { *(.rela.rodata)	}
-	.rel.got       : { *(.rel.got)		}
-	.rela.got      : { *(.rela.got)		}
-	.rel.ctors     : { *(.rel.ctors)	}
-	.rela.ctors    : { *(.rela.ctors)	}
-	.rel.dtors     : { *(.rel.dtors)	}
-	.rela.dtors    : { *(.rela.dtors)	}
-	.rel.bss       : { *(.rel.bss)		}
-	.rela.bss      : { *(.rela.bss)		}
-	.rel.plt       : { *(.rel.plt)		}
-	.rela.plt      : { *(.rela.plt)		}
-	.init          : { *(.init)		}
-	.plt : { *(.plt) }
-
-	.text : {
-		_load_addr = .;
-		_text = .;
-
-		*(.start)
-		arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
-		. = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
-		__prom_start = .;
-		*(.prom.pgt)
-		*(.prom.data)
-		*(.prom.text)
-		. = ALIGN(16);
-		__prom_end = .;
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-/*		*(.got1)*/
-		. = ALIGN(16);
-		*(.eh_frame)
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	_etext = .;
-
-	/* CMD Table */
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	.data	:
-	{
-		*(.data)
-		*(.data1)
-		*(.data.rel)
-		*(.data.rel.*)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	}
-	_edata	=	.;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__got_start = .;
-	.got : {
-		*(.got)
-/*		*(.data.rel)
-		*(.data.rel.local)*/
-		. = ALIGN(16);
-	}
-	__got_end = .;
-
-/*	.data.rel : { } */
-
-
-	. = ALIGN(4096);
-	__init_begin = .;
-	.text.init : { *(.text.init) }
-	.data.init : { *(.data.init) }
-	. = ALIGN(4096);
-	__init_end = .;
-
-	__bss_start = .;
-	.bss		:
-	{
-	 *(.sbss) *(.scommon)
-	 *(.dynbss)
-	 *(.bss)
-	 *(COMMON)
-	. = ALIGN(16); /* to speed clearing of bss up */
-	}
-	__bss_end = . ;
-	__bss_end = . ;
-	PROVIDE (end = .);
-
-/* Relocated into main memory */
-
-	/* Start of main memory */
-	/*. = 0x40000000;*/
-
-	.stack (NOLOAD)	: { *(.stack) }
-
-	/* PROM CODE */
-
-	/* global data in RAM passed to kernel after booting */
-
-
-  .stab 0		: { *(.stab) }
-  .stabstr 0		: { *(.stabstr) }
-  .stab.excl 0		: { *(.stab.excl) }
-  .stab.exclstr 0	: { *(.stab.exclstr) }
-  .stab.index 0		: { *(.stab.index) }
-  .stab.indexstr 0	: { *(.stab.indexstr) }
-  .comment 0		: { *(.comment) }
-
-}
diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds
deleted file mode 100644
index 1f038bca47..0000000000
--- a/board/gaisler/grsim_leon2/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GRSIM LEON2 simulator.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
-	. = + SIZEOF_HEADERS;
-	.interp : { *(.interp) }
-	.hash          : { *(.hash) }
-	.dynsym        : { *(.dynsym) }
-	.dynstr        : { *(.dynstr) }
-	.rel.text      : { *(.rel.text) }
-	.rela.text     : { *(.rela.text) }
-	.rel.data      : { *(.rel.data) }
-	.rela.data     : { *(.rela.data) }
-	.rel.rodata    : { *(.rel.rodata) }
-	.rela.rodata   : { *(.rela.rodata) }
-	.rel.got       : { *(.rel.got) }
-	.rela.got      : { *(.rela.got) }
-	.rel.ctors     : { *(.rel.ctors) }
-	.rela.ctors    : { *(.rela.ctors) }
-	.rel.dtors     : { *(.rel.dtors) }
-	.rela.dtors    : { *(.rela.dtors) }
-	.rel.bss       : { *(.rel.bss) }
-	.rela.bss      : { *(.rela.bss) }
-	.rel.plt       : { *(.rel.plt) }
-	.rela.plt      : { *(.rela.plt) }
-	.init          : { *(.init) }
-	.plt : { *(.plt) }
-
-	.text : {
-		_load_addr = .;
-		_text = .;
-
-		*(.start)
-		arch/sparc/cpu/leon2/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
-		. = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
-		__prom_start = .;
-		*(.prom.pgt)
-		*(.prom.data)
-		*(.prom.text)
-		. = ALIGN(16);
-		__prom_end = .;
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-/*		*(.got1)*/
-		. = ALIGN(16);
-		*(.eh_frame)
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-	. = ALIGN(4);
-	_etext = .;
-
-	/* CMD Table */
-
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	.data	:
-	{
-		*(.data)
-		*(.data1)
-		*(.data.rel)
-		*(.data.rel.*)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	}
-	_edata	=	.;
-	PROVIDE (edata = .);
-
-	. = ALIGN(4);
-	__got_start = .;
-	.got : {
-		*(.got)
-/*		*(.data.rel)
-		*(.data.rel.local)*/
-		. = ALIGN(16);
-	}
-	__got_end = .;
-
-/*	.data.rel : { } */
-
-	. = ALIGN(4096);
-	__init_begin = .;
-	.text.init : { *(.text.init) }
-	.data.init : { *(.data.init) }
-	. = ALIGN(4096);
-	__init_end = .;
-
-	__bss_start = .;
-	.bss	:
-	{
-	 *(.sbss) *(.scommon)
-	 *(.dynbss)
-	 *(.bss)
-	 *(COMMON)
-	. = ALIGN(16); /* to speed clearing of bss up */
-	}
-	__bss_end = . ;
-	__bss_end = . ;
-	PROVIDE (end = .);
-
-/* Relocated into main memory */
-
-	/* Start of main memory */
-	/*. = 0x40000000;*/
-
-	.stack (NOLOAD)	: { *(.stack) }
-
-	/* PROM CODE */
-
-	/* global data in RAM passed to kernel after booting */
-
-	.stab 0		: { *(.stab) }
-	.stabstr 0		: { *(.stabstr) }
-	.stab.excl 0		: { *(.stab.excl) }
-	.stab.exclstr 0	: { *(.stab.exclstr) }
-	.stab.index 0		: { *(.stab.index) }
-	.stab.indexstr 0	: { *(.stab.indexstr) }
-	.comment 0		: { *(.comment) }
-
-}
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
index 75aac49fd0..f644f8188b 100644
--- a/board/gumstix/pepper/board.c
+++ b/board/gumstix/pepper/board.c
@@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-			  (MT47H128M16RT25E_RD_DQS<<20) |
-			  (MT47H128M16RT25E_RD_DQS<<10) |
-			  (MT47H128M16RT25E_RD_DQS<<0)),
-	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-			  (MT47H128M16RT25E_WR_DQS<<20) |
-			  (MT47H128M16RT25E_WR_DQS<<10) |
-			  (MT47H128M16RT25E_WR_DQS<<0)),
-	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
-	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
+	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
 static const struct emif_regs ddr2_emif_reg_data = {
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
index 1b5487b144..99de2cad66 100644
--- a/board/mpl/common/kbd.c
+++ b/board/mpl/common/kbd.c
@@ -204,8 +204,6 @@ int drv_isa_kbd_init (void)
 	memset (&kbddev, 0, sizeof(kbddev));
 	strcpy(kbddev.name, DEVNAME);
 	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-	kbddev.putc = NULL ;
-	kbddev.puts = NULL ;
 	kbddev.getc = kbd_getc ;
 	kbddev.tstc = kbd_testc ;
 
@@ -250,7 +248,7 @@ void kbd_put_queue(char data)
 }
 
 /* test if a character is in the queue */
-int kbd_testc(void)
+int kbd_testc(struct stdio_dev *dev)
 {
 	if(in_pointer==out_pointer)
 		return(0); /* no data */
@@ -258,7 +256,7 @@ int kbd_testc(void)
 		return(1);
 }
 /* gets the character from the queue */
-int kbd_getc(void)
+int kbd_getc(struct stdio_dev *dev)
 {
 	char c;
 	while(in_pointer==out_pointer);
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
index 7b19b37259..b549e20ea4 100644
--- a/board/mpl/common/kbd.h
+++ b/board/mpl/common/kbd.h
@@ -8,8 +8,10 @@
 #ifndef _KBD_H_
 #define _KBD_H_
 
-extern int kbd_testc(void);
-extern int kbd_getc(void);
+struct stdio_dev;
+
+int kbd_testc(struct stdio_dev *sdev);
+int kbd_getc(struct stdio_dev *sdev);
 extern void kbd_interrupt(void);
 extern char *kbd_initialize(void);
 
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 8ca9bb31d0..5d701a7931 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -445,7 +445,7 @@ void pci_con_put_it(const char c)
 	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
 }
 
-void pci_con_putc(const char c)
+void pci_con_putc(struct stdio_dev *dev, const char c)
 {
 	pci_con_put_it(c);
 	if(c == '\n')
@@ -453,7 +453,7 @@ void pci_con_putc(const char c)
 }
 
 
-int pci_con_getc(void)
+int pci_con_getc(struct stdio_dev *dev)
 {
 	int res;
 	int diff;
@@ -473,14 +473,14 @@ int pci_con_getc(void)
 	return res;
 }
 
-int pci_con_tstc(void)
+int pci_con_tstc(struct stdio_dev *dev)
 {
 	if(r_ptr==(volatile int)w_ptr)
 		return 0;
 	return 1;
 }
 
-void pci_con_puts (const char *s)
+void pci_con_puts(struct stdio_dev *dev, const char *s)
 {
 	while (*s) {
 		pci_con_putc(*s);
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 3e419efe39..c2e07dbd9b 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -585,7 +585,7 @@ static void rx51_kp_fill(u8 k, u8 mods)
  * Routine: rx51_kp_tstc
  * Description: Test if key was pressed (from buffer).
  */
-int rx51_kp_tstc(void)
+int rx51_kp_tstc(struct stdio_dev *sdev)
 {
 	u8 c, r, dk, i;
 	u8 intr;
@@ -641,10 +641,10 @@ int rx51_kp_tstc(void)
  * Routine: rx51_kp_getc
  * Description: Get last pressed key (from buffer).
  */
-int rx51_kp_getc(void)
+int rx51_kp_getc(struct stdio_dev *sdev)
 {
 	keybuf_head %= KEYBUF_SIZE;
-	while (!rx51_kp_tstc())
+	while (!rx51_kp_tstc(sdev))
 		WATCHDOG_RESET();
 	return keybuf[keybuf_head++];
 }
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
index f33fae9170..220bb90dc1 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -16,7 +16,9 @@
 
 #include <common.h>
 #include <config.h>
+#include <fdt_support.h>
 #include <lcd.h>
+#include <mmc.h>
 #include <asm/arch/mbox.h>
 #include <asm/arch/sdhci.h>
 #include <asm/global_data.h>
@@ -91,7 +93,7 @@ int board_init(void)
 	return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
 }
 
-int board_mmc_init(void)
+int board_mmc_init(bd_t *bis)
 {
 	ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
 	int ret;
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
new file mode 100644
index 0000000000..9ed12bd87d
--- /dev/null
+++ b/board/renesas/alt/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= alt.o qos.o
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
new file mode 100644
index 0000000000..9d8e8f96be
--- /dev/null
+++ b/board/renesas/alt/alt.c
@@ -0,0 +1,173 @@
+/*
+ * board/renesas/alt/alt.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+}
+
+#define MSTPSR1		0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7		0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP719	(1 << 19)
+
+#define MSTPSR8		0xE61509A0
+#define SMSTPCR8	0xE6150990
+#define ETHER_MSTP813	(1 << 13)
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+	mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)   \
+	mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+
+	/* ETHER */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+	return 0;
+}
+
+void arch_preboot_os(void)
+{
+	/* Disable TMU0 */
+	mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7794_pinmux_init();
+
+	/* Ether Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ8, NULL);
+
+	/* PHY reset */
+	gpio_request(GPIO_GP_1_24, NULL);
+	gpio_direction_output(GPIO_GP_1_24, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_1_24, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+		enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	u8 val;
+
+	i2c_set_bus_num(1); /* PowerIC connected to ch3 */
+	i2c_init(400000, 0);
+	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	val |= 0x02;
+	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
new file mode 100644
index 0000000000..ea51f3f532
--- /dev/null
+++ b/board/renesas/alt/qos.c
@@ -0,0 +1,944 @@
+/*
+ * board/renesas/alt/qos.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.10 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	writel(0x1F0D0B0A, &s3c->s3crorr);
+	writel(0x1F0D0B09, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80928092, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x0000202A, &qos_addr->dbtmval2);
+		writel(0x00001FBD, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x0000207D, &qos_addr->dbtmval0);
+		writel(0x00002053, &qos_addr->dbtmval1);
+		writel(0x00002043, &qos_addr->dbtmval2);
+		writel(0x00002030, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002064, &qos_addr->dbthres0);
+		writel(0x0000203E, &qos_addr->dbthres1);
+		writel(0x00002031, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000E, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000040, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020EB, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00001FF0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00002001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000003, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosthres0);
+	writel(0x00000001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
diff --git a/board/renesas/alt/qos.h b/board/renesas/alt/qos.h
new file mode 100644
index 0000000000..9a6c0461be
--- /dev/null
+++ b/board/renesas/alt/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index cbf8f086a9..62acb8ff27 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,4 +10,8 @@
 #
 obj-y	+= board.o
 obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
+obj-$(CONFIG_A13_OLINUXINOM)	+= dram_a13_oli_micro.o
+obj-$(CONFIG_CUBIEBOARD)	+= dram_cubieboard.o
+obj-$(CONFIG_CUBIEBOARD2)	+= dram_cubieboard2.o
 obj-$(CONFIG_CUBIETRUCK)	+= dram_cubietruck.o
+obj-$(CONFIG_R7DONGLE)		+= dram_r7dongle.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b05d0b9b18..2179e234e2 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,10 +12,19 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
 #include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/io.h>
+#include <net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -106,15 +115,73 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+void i2c_init_board(void)
+{
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+	clock_twi_onoff(0, 1);
+}
+
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {
+	int power_failed = 0;
 	unsigned long ramsize;
 
+#ifdef CONFIG_AXP152_POWER
+	power_failed = axp152_init();
+	power_failed |= axp152_set_dcdc2(1400);
+	power_failed |= axp152_set_dcdc3(1500);
+	power_failed |= axp152_set_dcdc4(1250);
+	power_failed |= axp152_set_ldo2(3000);
+#endif
+#ifdef CONFIG_AXP209_POWER
+	power_failed |= axp209_init();
+	power_failed |= axp209_set_dcdc2(1400);
+	power_failed |= axp209_set_dcdc3(1250);
+	power_failed |= axp209_set_ldo2(3000);
+	power_failed |= axp209_set_ldo3(2800);
+	power_failed |= axp209_set_ldo4(2800);
+#endif
+
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
 	printf(" %lu MiB\n", ramsize >> 20);
 	if (!ramsize)
 		hang();
+
+	/*
+	 * Only clock up the CPU to full speed if we are reasonably
+	 * assured it's being powered with suitable core voltage
+	 */
+	if (!power_failed)
+		clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	if (!getenv("ethaddr")) {
+		uint32_t reg_val = readl(SUNXI_SID_BASE);
+
+		if (reg_val) {
+			uint8_t mac_addr[6];
+
+			mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
+			mac_addr[1] = (reg_val >>  0) & 0xff;
+			reg_val = readl(SUNXI_SID_BASE + 0x0c);
+			mac_addr[2] = (reg_val >> 24) & 0xff;
+			mac_addr[3] = (reg_val >> 16) & 0xff;
+			mac_addr[4] = (reg_val >>  8) & 0xff;
+			mac_addr[5] = (reg_val >>  0) & 0xff;
+
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		}
+	}
+
+	return 0;
 }
 #endif
diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c
new file mode 100644
index 0000000000..8154ea2ca9
--- /dev/null
+++ b/board/sunxi/dram_a13_oli_micro.c
@@ -0,0 +1,32 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 408,
+	.type = 3,
+	.rank_num = 1,
+	.density = 2048,
+	.io_width = 16,
+	.bus_width = 16,
+	.cas = 9,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 256,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0,
+	.emr2 = 0x10,
+	.emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
new file mode 100644
index 0000000000..399028ca96
--- /dev/null
+++ b/board/sunxi/dram_cubieboard.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 480,
+	.type = 3,
+	.rank_num = 1,
+	.density = 4096,
+	.io_width = 16,
+	.bus_width = 32,
+	.cas = 6,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x30926692,
+	.tpr1 = 0x1090,
+	.tpr2 = 0x1a0c8,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0,
+	.emr2 = 0,
+	.emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c
new file mode 100644
index 0000000000..9e753677c5
--- /dev/null
+++ b/board/sunxi/dram_cubieboard2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 480,
+	.type = 3,
+	.rank_num = 1,
+	.density = 4096,
+	.io_width = 16,
+	.bus_width = 32,
+	.cas = 9,
+	.zq = 0x7f,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0x0,
+	.tpr4 = 0x1,
+	.tpr5 = 0x0,
+	.emr1 = 0x4,
+	.emr2 = 0x10,
+	.emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c
new file mode 100644
index 0000000000..59343cb2a5
--- /dev/null
+++ b/board/sunxi/dram_r7dongle.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 384,
+	.type = 3,
+	.rank_num = 1,
+	.density = 2048,
+	.io_width = 8,
+	.bus_width = 32,
+	.cas = 9,
+	.zq = 123,
+	.odt_en = 0,
+	.size = 1024,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0,
+	.tpr4 = 0,
+	.tpr5 = 0,
+	.emr1 = 0x04,
+	.emr2 = 0x10,
+	.emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e48328d9e8..e7ff95285c 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
 	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 
 	/* Set MII clock */
+#ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
 		CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+		CCM_GMAC_CTRL_GPIT_MII);
+#endif
 
 	/* Configure pin mux settings for GMAC */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
 		/* skip unused pins in RGMII mode */
 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
 			continue;
+#endif
 		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 
+#ifdef CONFIG_RGMII
 	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
 }
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index da780edb89..d81eec90b4 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-			  (MT47H128M16RT25E_RD_DQS<<20) |
-			  (MT47H128M16RT25E_RD_DQS<<10) |
-			  (MT47H128M16RT25E_RD_DQS<<0)),
-	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-			  (MT47H128M16RT25E_WR_DQS<<20) |
-			  (MT47H128M16RT25E_WR_DQS<<10) |
-			  (MT47H128M16RT25E_WR_DQS<<0)),
-	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
-	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
+	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
 static const struct emif_regs ddr2_emif_reg_data = {
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 7e239f1c88..51fa9e04a3 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <power/pmic.h>
 #include <power/tps65218.h>
 #include <miiphy.h>
 #include <cpsw.h>
@@ -605,6 +606,19 @@ void sdram_init(void)
 }
 #endif
 
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+
+	power_tps65218_init(I2C_PMIC);
+	p = pmic_get("TPS65218_PMIC");
+	if (p && !pmic_probe(p))
+		puts("PMIC:  TPS65218\n");
+
+	return 0;
+}
+
 int board_init(void)
 {
 	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7f19655cfe..ae50d88c57 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -163,6 +163,8 @@ int spl_start_uboot(void)
 #define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
 #define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)
 
+extern u32 *const omap_si_rev;
+
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */
@@ -189,7 +191,7 @@ static struct cpsw_platform_data cpsw_data = {
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
+	.slaves			= 2,
 	.slave_data		= cpsw_slaves,
 	.ale_reg_ofs		= 0xd00,
 	.ale_entries		= 1024,
@@ -260,6 +262,9 @@ int board_eth_init(bd_t *bis)
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
+	if (*omap_si_rev == DRA722_ES1_0)
+		cpsw_data.active_slave = 1;
+
 	ret = cpsw_register(&cpsw_data);
 	if (ret < 0)
 		printf("Error %d registering CPSW switch\n", ret);
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c9e202af68..7db70324e9 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -56,6 +56,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+	{VIN2A_D12, (M3) },
+	{VIN2A_D13, (M3) },
+	{VIN2A_D14, (M3) },
+	{VIN2A_D15, (M3) },
+	{VIN2A_D16, (M3) },
+	{VIN2A_D17, (M3) },
+	{VIN2A_D18, (IEN | M3)},
+	{VIN2A_D19, (IEN | M3)},
+	{VIN2A_D20, (IEN | M3)},
+	{VIN2A_D21, (IEN | M3)},
+	{VIN2A_D22, (IEN | M3)},
+	{VIN2A_D23, (IEN | M3)},
 	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
 	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
 	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile
deleted file mode 100644
index 3645f2feb0..0000000000
--- a/board/ti/k2hk_evm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# K2HK-EVM: board Makefile
-# (C) Copyright 2012-2014
-#     Texas Instruments Incorporated, <www.ti.com>
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= board.o
-obj-y	+= ddr3.o
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
deleted file mode 100644
index 6092eb8fe3..0000000000
--- a/board/ti/k2hk_evm/ddr3.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
-	.sdcfg		= 0x6200CE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
-	.sdcfg		= 0x6200DE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0x70073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
-	.sdcfg		= 0x62008C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
-	.sdcfg		= 0x62009C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xf0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-/******************************************************/
-int get_dimm_params(char *dimm_name)
-{
-	u8 spd_params[256];
-	int ret;
-	int old_bus;
-
-	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
-	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
-	i2c_set_bus_num(old_bus);
-
-	dimm_name[0] = '\0';
-
-	if (ret) {
-		puts("Cannot read DIMM params\n");
-		return 1;
-	}
-
-	/*
-	 * We need to convert spd data to dimm parameters
-	 * and to DDR3 EMIF and PHY regirsters values.
-	 * For now we just return DIMM type string value.
-	 * Caller may use this value to choose appropriate
-	 * a pre-set DDR3 configuration
-	 */
-
-	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
-	dimm_name[18] = '\0';
-
-	return 0;
-}
-
-struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
-struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-
-void init_ddr3(void)
-{
-	char dimm_name[32];
-
-	get_dimm_params(dimm_name);
-
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
-
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		init_pll(&ddr3a_400);
-		if (cpu_revision() > 0) {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
-			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
-		} else {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
-			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
-		}
-	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
-		init_pll(&ddr3a_333);
-		if (cpu_revision() > 0) {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
-		} else {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
-		}
-	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
-	}
-
-	init_pll(&ddr3b_333);
-	init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
-	init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
-}
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
new file mode 100644
index 0000000000..00f1164833
--- /dev/null
+++ b/board/ti/ks2_evm/Makefile
@@ -0,0 +1,13 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3_cfg.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
diff --git a/board/ti/k2hk_evm/README b/board/ti/ks2_evm/README_K2HK
index bfeb05b4a4..7426b8dc97 100644
--- a/board/ti/k2hk_evm/README
+++ b/board/ti/ks2_evm/README_K2HK
@@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h
 
 Supported boot modes:
  - SPI NOR boot
+ - AEMIF NAND boot
 
 Supported image formats:-
  - u-boot.bin: for loading and running u-boot.bin through Texas instruments
                code composure studio (CCS)
  - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
 
 Build instructions:
 ===================
@@ -55,6 +57,10 @@ To build u-boot-spi.gph
   >make k2hk_evm_config
   >make u-boot-spi.gph
 
+To build u-boot-nand.gph
+  >make k2hk_evm_config
+  >make u-boot-nand.gph
+
 Load and Run U-Boot on K2HK EVM using CCS
 =========================================
 
@@ -115,8 +121,28 @@ instructions:-
 5. At the U-Boot console type following to setup u-boot environment variables.
    setenv addr_uboot 0x87000000
    setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
-   run burn_uboot
+   run burn_uboot_spi
    Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
    to "SPI Little Endian Boot mode" as per instruction at
    http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
 6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+   CortexA15_1 (Free Running)"
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
+   through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+   using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+   setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
+   run burn_uboot_nand
+   Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+   to "ARM NAND Boot mode" as per instruction at
+   http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/ks2_evm/board.c
index ef90f9d821..dfe7be60e7 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -1,45 +1,22 @@
 /*
- * K2HK EVM : Board initialization
+ * Keystone : Board initialization
  *
- * (C) Copyright 2012-2014
+ * (C) Copyright 2014
  *     Texas Instruments Incorporated, <www.ti.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include "board.h"
 #include <common.h>
 #include <exports.h>
 #include <fdt_support.h>
-#include <libfdt.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
+#include <asm/arch/ddr3.h>
 #include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/ti-aemif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 device_big_endian;
-
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	=	122880000,
-	[alt_core_clk]	=	125000000,
-	[pa_clk]	=	122880000,
-	[tetris_clk]	=	125000000,
-	[ddr3a_clk]	=	100000000,
-	[ddr3b_clk]	=	100000000,
-	[mcm_clk]	=	312500000,
-	[pcie_clk]	=	100000000,
-	[sgmii_srio_clk] =	156250000,
-	[xgmii_clk]	=	156250000,
-	[usb_clk]	=	100000000,
-	[rp1_clk]	=	123456789    /* TODO: cannot find
-						what is that */
-};
-
 static struct aemif_config aemif_configs[] = {
 	{			/* CS0 */
 		.mode		= AEMIF_MODE_NAND,
@@ -52,18 +29,11 @@ static struct aemif_config aemif_configs[] = {
 		.turn_around	= 3,
 		.width		= AEMIF_WIDTH_8,
 	},
-
-};
-
-static struct pll_init_data pll_config[] = {
-	CORE_PLL_1228,
-	PASS_PLL_983,
-	TETRIS_PLL_1200,
 };
 
 int dram_init(void)
 {
-	init_ddr3();
+	ddr3_init();
 
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
@@ -71,42 +41,18 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-	{
-		.int_name	= "K2HK_EMAC",
-		.rx_flow	= 22,
-		.phy_addr	= 0,
-		.slave_port	= 1,
-		.sgmii_link_type = SGMII_LINK_MAC_PHY,
-	},
-	{
-		.int_name	= "K2HK_EMAC1",
-		.rx_flow	= 23,
-		.phy_addr	= 1,
-		.slave_port	= 2,
-		.sgmii_link_type = SGMII_LINK_MAC_PHY,
-	},
-	{
-		.int_name	= "K2HK_EMAC2",
-		.rx_flow	= 24,
-		.phy_addr	= 2,
-		.slave_port	= 3,
-		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-	},
-	{
-		.int_name	= "K2HK_EMAC3",
-		.rx_flow	= 25,
-		.phy_addr	= 3,
-		.slave_port	= 4,
-		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-	},
-};
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+
+	return 0;
+}
 
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 int get_eth_env_param(char *env_name)
 {
 	char *env;
-	int  res = -1;
+	int res = -1;
 
 	env = getenv(env_name);
 	if (env)
@@ -117,12 +63,14 @@ int get_eth_env_param(char *env_name)
 
 int board_eth_init(bd_t *bis)
 {
-	int	j;
-	int	res;
-	char	link_type_name[32];
+	int j;
+	int res;
+	int port_num;
+	char link_type_name[32];
 
-	for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
-	     j++) {
+	port_num = get_num_eth_ports();
+
+	for (j = 0; j < port_num; j++) {
 		sprintf(link_type_name, "sgmii%d_link_type", j);
 		res = get_eth_env_param(link_type_name);
 		if (res >= 0)
@@ -135,46 +83,24 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
-	u32 i;
-
-	if (device_big_endian)
-		for (i = 0; i < length; i++, ptr++)
-			*ptr = __swab32(*ptr);
-
-	return 0;
-}
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
-{
-	init_plls(ARRAY_SIZE(pll_config), pll_config);
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-#define K2_DDR3_START_ADDR 0x80000000
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	u64 start[2];
+	int lpae;
+	char *env;
+	char *endp;
+	int nbanks;
 	u64 size[2];
-	char name[32], *env, *endp;
-	int lpae, nodeoffset;
+	u64 start[2];
+	char name[32];
+	int nodeoffset;
 	u32 ddr3a_size;
-	int nbanks;
+	int unitrd_fixup = 0;
 
 	env = getenv("mem_lpae");
 	lpae = env && simple_strtol(env, NULL, 0);
+	env = getenv("uinitrd_fixup");
+	unitrd_fixup = env && simple_strtol(env, NULL, 0);
 
 	ddr3a_size = 0;
 	if (lpae) {
@@ -191,7 +117,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	/* adjust memory start address for LPAE */
 	if (lpae) {
-		start[0] -= K2_DDR3_START_ADDR;
+		start[0] -= CONFIG_SYS_SDRAM_BASE;
 		start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 	}
 
@@ -217,10 +143,11 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory_banks(blob, start, size, nbanks);
 
 	/* Fix up the initrd */
-	if (lpae) {
-		u64 initrd_start, initrd_end;
-		u32 *prop1, *prop2;
+	if (lpae && unitrd_fixup) {
 		int err;
+		u32 *prop1, *prop2;
+		u64 initrd_start, initrd_end;
+
 		nodeoffset = fdt_path_offset(blob, "/chosen");
 		if (nodeoffset >= 0) {
 			prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
@@ -229,11 +156,11 @@ void ft_board_setup(void *blob, bd_t *bd)
 					    "linux,initrd-end", NULL);
 			if (prop1 && prop2) {
 				initrd_start = __be32_to_cpu(*prop1);
-				initrd_start -= K2_DDR3_START_ADDR;
+				initrd_start -= CONFIG_SYS_SDRAM_BASE;
 				initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 				initrd_start = __cpu_to_be64(initrd_start);
 				initrd_end = __be32_to_cpu(*prop2);
-				initrd_end -= K2_DDR3_START_ADDR;
+				initrd_end -= CONFIG_SYS_SDRAM_BASE;
 				initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 				initrd_end = __cpu_to_be64(initrd_end);
 
@@ -267,9 +194,10 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 void ft_board_setup_ex(void *blob, bd_t *bd)
 {
-	int	lpae;
-	char	*env;
-	u64	*reserve_start, size;
+	int lpae;
+	u64 size;
+	char *env;
+	u64 *reserve_start;
 
 	env = getenv("mem_lpae");
 	lpae = env && simple_strtol(env, NULL, 0);
@@ -286,7 +214,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 			*reserve_start = __cpu_to_be64(*reserve_start);
 			size = __cpu_to_be64(*(reserve_start + 1));
 			if (size) {
-				*reserve_start -= K2_DDR3_START_ADDR;
+				*reserve_start -= CONFIG_SYS_SDRAM_BASE;
 				*reserve_start +=
 					CONFIG_SYS_LPAE_SDRAM_BASE;
 				*reserve_start =
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
new file mode 100644
index 0000000000..d91ef73612
--- /dev/null
+++ b/board/ti/ks2_evm/board.h
@@ -0,0 +1,19 @@
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/arch/emac_defs.h>
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int get_num_eth_ports(void);
+
+#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
new file mode 100644
index 0000000000..d2499b7244
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -0,0 +1,39 @@
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	= 100000000,
+	[alt_core_clk]	= 100000000,
+	[pa_clk]	= 100000000,
+	[ddr3_clk]	= 100000000,
+	[mcm_clk]	= 312500000,
+	[pcie_clk]	= 100000000,
+	[sgmii_clk]	= 156250000,
+	[xgmii_clk]	= 156250000,
+	[usb_clk]	= 100000000,
+};
+
+static struct pll_init_data pll_config[] = {
+	CORE_PLL_1200,
+	PASS_PLL_1000,
+};
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+	return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
new file mode 100644
index 0000000000..a369d6bd63
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -0,0 +1,81 @@
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	=	122880000,
+	[alt_core_clk]	=	125000000,
+	[pa_clk]	=	122880000,
+	[tetris_clk]	=	125000000,
+	[ddr3a_clk]	=	100000000,
+	[ddr3b_clk]	=	100000000,
+	[mcm_clk]	=	312500000,
+	[pcie_clk]	=	100000000,
+	[sgmii_srio_clk] =	156250000,
+	[xgmii_clk]	=	156250000,
+	[usb_clk]	=	100000000,
+	[rp1_clk]	=	123456789
+};
+
+static struct pll_init_data pll_config[] = {
+	CORE_PLL_1228,
+	PASS_PLL_983,
+	TETRIS_PLL_1200,
+};
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+	{
+		.int_name	= "K2HK_EMAC",
+		.rx_flow	= 22,
+		.phy_addr	= 0,
+		.slave_port	= 1,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name	= "K2HK_EMAC1",
+		.rx_flow	= 23,
+		.phy_addr	= 1,
+		.slave_port	= 2,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name	= "K2HK_EMAC2",
+		.rx_flow	= 24,
+		.phy_addr	= 2,
+		.slave_port	= 3,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name	= "K2HK_EMAC3",
+		.rx_flow	= 25,
+		.phy_addr	= 3,
+		.slave_port	= 4,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+};
+
+int get_num_eth_ports(void)
+{
+	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+	return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 0000000000..f7da9f2bcb
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,170 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0D861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0xA19DBB66ul,
+	.dtpr1          = 0x32868300ul,
+	.dtpr2          = 0x50035200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x730035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+	.sdcfg          = 0x6200CE6Aul,
+	.sdtim1         = 0x16709C55ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x435DFF54ul,
+	.sdtim4         = 0x553F0CFFul,
+	.zqcfg          = 0xF0073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+	.pllcr          = 0x0005C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0B4515C2ul,
+	.ptr4           = 0x0A6E08B4ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x8558AA55ul,
+	.dtpr1          = 0x32857280ul,
+	.dtpr2          = 0x5002C200ul,
+	.mr0            = 0x00001A60ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000010ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F065B8ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+	.sdcfg          = 0x62008C62ul,
+	.sdtim1         = 0x125C8044ul,
+	.sdtim2         = 0x00001D29ul,
+	.sdtim3         = 0x32CDFF43ul,
+	.sdtim4         = 0x543F0ADFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001457ul,
+};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+/* DDR3 PHY configuration data with 1600M rate, and 4GB size  */
+struct ddr3_phy_config ddr3phy_1600_4g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x08861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x9D9CBB66ul,
+	.dtpr1          = 0x12840300ul,
+	.dtpr2          = 0x5002D200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, and 4GB size  */
+struct ddr3_emif_config ddr3_1600_4g = {
+	.sdcfg          = 0x6200CE62ul,
+	.sdtim1         = 0x166C9855ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x421DFF53ul,
+	.sdtim4         = 0x543F07FFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+	int ret;
+	int old_bus;
+	u8 spd_params[256];
+
+	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+	old_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+	i2c_set_bus_num(old_bus);
+
+	dimm_name[0] = '\0';
+
+	if (ret) {
+		puts("Cannot read DIMM params\n");
+		return 1;
+	}
+
+	/*
+	 * We need to convert spd data to dimm parameters
+	 * and to DDR3 EMIF and PHY regirsters values.
+	 * For now we just return DIMM type string value.
+	 * Caller may use this value to choose appropriate
+	 * a pre-set DDR3 configuration
+	 */
+
+	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+	dimm_name[18] = '\0';
+
+	return 0;
+}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 0000000000..15fcf52ef1
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,24 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+extern struct ddr3_phy_config ddr3phy_1600_4g;
+extern struct ddr3_emif_config ddr3_1600_4g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
new file mode 100644
index 0000000000..40fd96607d
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -0,0 +1,55 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+	char dimm_name[32];
+
+	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
+		init_pll(&ddr3_400);
+
+	ddr3_get_dimm_params(dimm_name);
+
+	printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+		/* 8G SO-DIMM */
+		ddr3_size = 8;
+		printf("DRAM: 8 GiB\n");
+		ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+		ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+		ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
+	} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
+		/* 4G SO-DIMM */
+		ddr3_size = 4;
+		printf("DRAM: 4 GiB\n");
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+	}
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+	return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
new file mode 100644
index 0000000000..21a5a0a252
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -0,0 +1,84 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+void ddr3_init(void)
+{
+	char dimm_name[32];
+
+	ddr3_get_dimm_params(dimm_name);
+
+	printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+		init_pll(&ddr3a_400);
+		if (cpu_revision() > 0) {
+			if (cpu_revision() > 1) {
+				/* PG 2.0 */
+				/* Reset DDR3A PHY after PLL enabled */
+				ddr3_reset_ddrphy();
+				ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1600_8g);
+			} else {
+				/* PG 1.1 */
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1600_8g);
+			}
+
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1600_8g);
+			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
+		} else {
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+			ddr3_1600_8g.sdcfg |= 0x1000;
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1600_8g);
+			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
+		}
+	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+		init_pll(&ddr3a_333);
+		if (cpu_revision() > 0) {
+			if (cpu_revision() > 1) {
+				/* PG 2.0 */
+				/* Reset DDR3A PHY after PLL enabled */
+				ddr3_reset_ddrphy();
+				ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq2cr1 |= 0x10000;
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1333_2g);
+			} else {
+				/* PG 1.1 */
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1333_2g);
+			}
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1333_2g);
+		} else {
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+			ddr3_1333_2g.sdcfg |= 0x1000;
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1333_2g);
+		}
+	} else {
+		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+		while (1)
+			;
+	}
+}
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index fd93f6317b..71c0c351f9 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -10,3 +10,6 @@ obj-y	:= board.o
 # Please copy ps7_init.c/h from hw project to this directory
 obj-$(CONFIG_SPL_BUILD) += \
 		$(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
diff --git a/boards.cfg b/boards.cfg
index 8a46be5a44..44dccbf2db 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -300,7 +300,8 @@ Active  arm         armv7          exynos      samsung         trats
 Active  arm         armv7          exynos      samsung         trats2              trats2                                -                                                                                                                                 Piotr Wilczek <p.wilczek@samsung.com>
 Active  arm         armv7          exynos      samsung         universal_c210      s5pc210_universal                     -                                                                                                                                 Przemyslaw Marczak <p.marczak@samsung.com>
 Active  arm         armv7          highbank    -               highbank            highbank                              -                                                                                                                                 Rob Herring <robh@kernel.org>
-Active  arm         armv7          keystone    ti              k2hk_evm            k2hk_evm                              -                                                                                                                                 Vitaly Andrianov <vitalya@ti.com>
+Active  arm         armv7          keystone    ti              ks2_evm             k2hk_evm                              -                                                                                                                                 Vitaly Andrianov <vitalya@ti.com>
+Active  arm         armv7          keystone    ti              ks2_evm		   k2e_evm                               -                                                                                                                                 Vitaly Andrianov <vitalya@ti.com>
 Active  arm         armv7          mx5         denx            m53evk              m53evk                                m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg                                                                                  Marek Vasut <marek.vasut@gmail.com>
 Active  arm         armv7          mx5         esg             ima3-mx53           ima3-mx53                             ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg                                                                             -
 Active  arm         armv7          mx5         freescale       mx51evk             mx51evk                               mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg                                                                           Stefano Babic <sbabic@denx.de>
@@ -378,13 +379,19 @@ Active  arm         armv7          omap5       ti              dra7xx
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                            -                                                                                                                                 Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          rmobile     atmark-techno   armadillo-800eva    armadillo-800eva                      -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     kmc             kzm9g               kzm9g                                 -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active  arm         armv7          rmobile     renesas         alt                 alt                                   -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     renesas         koelsch             koelsch                               -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     renesas         lager               lager                                 -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                              -                                                                                                                                 Robert Baldyga <r.baldyga@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                              -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                      -                                                                                                                                 -
-Active  arm         armv7          sunxi       -               sunxi               Cubietruck                            sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII                                                                                             -
-Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                        sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII                                                                                         -
+Active  arm         armv7          sunxi       -               sunxi               A13-OLinuXinoM                        sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2                                                                                             Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               Cubieboard                            sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC                                                                                      Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               Cubieboard2                           sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC                                                                                                  Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               Cubieboard2_FEL                       sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC                                                                                              Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck                            sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII                                                                                Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                        sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII                                                                            Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active  arm         armv7          sunxi       -               sunxi               r7-tv-dongle                          sun5i:R7DONGLE,SPL,AXP152_POWER                                                                                                   Hans de Goede <hdegoede@redhat.com>
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                              -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                            -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                              vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
@@ -1013,19 +1020,19 @@ Active  powerpc     mpc8xx         -           tqc             tqm8xx
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TK885D                                -                                                                                                                                 -
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823L                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823L_LCD                           TQM823L:LCD,NEC_NL6448BC20                                                                                                        Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823M                               -                                                                                                                                 -
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM823M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM850L                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM850M                               -                                                                                                                                 -
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM850M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM855L                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM855M                               -                                                                                                                                 -
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM855M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM860L                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM860M                               -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862L                               -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862M                               -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM866M                               -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM885D                               -                                                                                                                                 -
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM860M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862L                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM862M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM866M                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              TQM885D                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              TTTech                                TQM823L:LCD,SHARP_LQ104V7DS01                                                                                                     Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           tqc             tqm8xx              virtlab2                              -                                                                                                                                 -
+Active  powerpc     mpc8xx         -           tqc             tqm8xx              virtlab2                              -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           tqc             tqm8xx              wtk                                   TQM823L:LCD,SHARP_LQ065T9DR51U                                                                                                    Wolfgang Denk <wd@denx.de>
 Active  powerpc     ppc4xx         -           -               csb272              csb272                                -                                                                                                                                 Tolunay Orkun <torkun@nextio.com>
 Active  powerpc     ppc4xx         -           -               csb472              csb472                                -                                                                                                                                 Tolunay Orkun <torkun@nextio.com>
diff --git a/common/autoboot.c b/common/autoboot.c
index 30102a47a8..c27cc2c751 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <autoboot.h>
 #include <bootretry.h>
 #include <cli.h>
 #include <fdtdec.h>
diff --git a/common/board_f.c b/common/board_f.c
index 4ea4cb21be..6203d85619 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -14,6 +14,7 @@
 #include <linux/compiler.h>
 #include <version.h>
 #include <environment.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <fs.h>
 #if defined(CONFIG_CMD_IDE)
@@ -37,6 +38,7 @@
 #include <os.h>
 #include <post.h>
 #include <spi.h>
+#include <status_led.h>
 #include <trace.h>
 #include <watchdog.h>
 #include <asm/errno.h>
@@ -52,6 +54,7 @@
 #ifdef CONFIG_SANDBOX
 #include <asm/state.h>
 #endif
+#include <dm/root.h>
 #include <linux/compiler.h>
 
 /*
@@ -78,25 +81,15 @@ DECLARE_GLOBAL_DATA_PTR;
  ************************************************************************
  * May be supplied by boards if desired
  */
-inline void __coloured_LED_init(void) {}
-void coloured_LED_init(void)
-	__attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_led_on(void) {}
-void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
-inline void __red_led_off(void) {}
-void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
-inline void __green_led_on(void) {}
-void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
-inline void __green_led_off(void) {}
-void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
-inline void __yellow_led_on(void) {}
-void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
-inline void __yellow_led_off(void) {}
-void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
-inline void __blue_led_on(void) {}
-void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
-inline void __blue_led_off(void) {}
-void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+__weak void coloured_LED_init(void) {}
+__weak void red_led_on(void) {}
+__weak void red_led_off(void) {}
+__weak void green_led_on(void) {}
+__weak void green_led_off(void) {}
+__weak void yellow_led_on(void) {}
+__weak void yellow_led_off(void) {}
+__weak void blue_led_on(void) {}
+__weak void blue_led_off(void) {}
 
 /*
  * Why is gd allocated a register? Prior to reloc it might be better to
@@ -776,6 +769,30 @@ static int mark_bootstage(void)
 	return 0;
 }
 
+static int initf_malloc(void)
+{
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	assert(gd->malloc_base);	/* Set up by crt0.S */
+	gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN;
+	gd->malloc_ptr = 0;
+#endif
+
+	return 0;
+}
+
+static int initf_dm(void)
+{
+#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+	int ret;
+
+	ret = dm_init_and_scan(true);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 static init_fnc_t init_sequence_f[] = {
 #ifdef CONFIG_SANDBOX
 	setup_ram_buf,
@@ -833,6 +850,8 @@ static init_fnc_t init_sequence_f[] = {
 	sdram_adjust_866,
 	init_timebase,
 #endif
+	initf_malloc,
+	initf_dm,
 	init_baud_rate,		/* initialze baudrate settings */
 	serial_init,		/* serial communications setup */
 	console_init_f,		/* stage 1 init of console */
diff --git a/common/board_r.c b/common/board_r.c
index 602a239380..8e7a3ac74c 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -259,6 +259,10 @@ static int initr_malloc(void)
 {
 	ulong malloc_start;
 
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+	      gd->malloc_ptr / 1024);
+#endif
 	/* The malloc area is immediately below the monitor copy in DRAM */
 	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
 	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
@@ -269,27 +273,10 @@ static int initr_malloc(void)
 #ifdef CONFIG_DM
 static int initr_dm(void)
 {
-	int ret;
-
-	ret = dm_init();
-	if (ret) {
-		debug("dm_init() failed: %d\n", ret);
-		return ret;
-	}
-	ret = dm_scan_platdata();
-	if (ret) {
-		debug("dm_scan_platdata() failed: %d\n", ret);
-		return ret;
-	}
-#ifdef CONFIG_OF_CONTROL
-	ret = dm_scan_fdt(gd->fdt_blob);
-	if (ret) {
-		debug("dm_scan_fdt() failed: %d\n", ret);
-		return ret;
-	}
-#endif
-
-	return 0;
+	/* Save the pre-reloc driver model and start a new one */
+	gd->dm_root_f = gd->dm_root;
+	gd->dm_root = NULL;
+	return dm_init_and_scan(false);
 }
 #endif
 
@@ -588,15 +575,12 @@ static int initr_status_led(void)
 #if defined(CONFIG_CMD_SCSI)
 static int initr_scsi(void)
 {
-	/* Not supported properly on ARM yet */
-#ifndef CONFIG_ARM
 	puts("SCSI:  ");
 	scsi_init();
-#endif
 
 	return 0;
 }
-#endif /* CONFIG_CMD_NET */
+#endif
 
 #if defined(CONFIG_CMD_DOC)
 static int initr_doc(void)
diff --git a/common/bootm_os.c b/common/bootm_os.c
index f7769ac853..5be4467a1c 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -437,11 +437,10 @@ static boot_os_fn *boot_os[] = {
 };
 
 /* Allow for arch specific config before we boot */
-static void __arch_preboot_os(void)
+__weak void arch_preboot_os(void)
 {
 	/* please define platform specific arch_preboot_os() */
 }
-void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
 
 int boot_selected_os(int argc, char * const argv[], int state,
 		     bootm_headers_t *images, boot_os_fn *boot_fn)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index f283a1616e..3d37a86a7d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -351,7 +351,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #elif defined(CONFIG_ARM)
 
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
 {
 	int i;
 	bd_t *bd = gd->bd;
diff --git a/common/cmd_cache.c b/common/cmd_cache.c
index 602fecaba2..37ab345cb6 100644
--- a/common/cmd_cache.c
+++ b/common/cmd_cache.c
@@ -20,7 +20,7 @@ void __weak invalidate_icache_all(void)
 	puts("No arch specific invalidate_icache_all available!\n");
 }
 
-int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	switch (argc) {
 	case 2:			/* on / off	*/
@@ -52,7 +52,7 @@ void __weak flush_dcache_all(void)
 	/* please define arch specific flush_dcache_all */
 }
 
-int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	switch (argc) {
 	case 2:			/* on / off */
diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c
index fad462fb34..a02f0cb0bb 100644
--- a/common/cmd_eeprom.c
+++ b/common/cmd_eeprom.c
@@ -43,7 +43,7 @@ extern int eeprom_write_enable (unsigned dev_addr, int state);
 /* ------------------------------------------------------------------------- */
 
 #if defined(CONFIG_CMD_EEPROM)
-int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	const char *const fmt =
 		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
@@ -413,7 +413,7 @@ U_BOOT_CMD(
 	"read  devaddr addr off cnt\n"
 	"eeprom write devaddr addr off cnt\n"
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
-);
+)
 #else /* One EEPROM */
 U_BOOT_CMD(
 	eeprom,	5,	1,	do_eeprom,
@@ -421,7 +421,7 @@ U_BOOT_CMD(
 	"read  addr off cnt\n"
 	"eeprom write addr off cnt\n"
 	"       - read/write `cnt' bytes at EEPROM offset `off'"
-);
+)
 #endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
 
 #endif
diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c
index 5a4bcc1a36..6657ef5ca4 100644
--- a/common/cmd_ext2.c
+++ b/common/cmd_ext2.c
@@ -22,7 +22,7 @@
  */
 #include <fs.h>
 
-int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT);
 }
@@ -30,7 +30,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 /******************************************************************************
  * Ext2fs boot command intepreter. Derived from diskboot
  */
-int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT);
 }
@@ -40,12 +40,12 @@ U_BOOT_CMD(
 	"list files in a directory (default /)",
 	"<interface> <dev[:part]> [directory]\n"
 	"    - list files from 'dev' on 'interface' in a 'directory'"
-);
+)
 
 U_BOOT_CMD(
 	ext2load,	6,	0,	do_ext2load,
 	"load binary file from a Ext2 filesystem",
-	"<interface> <dev[:part]> [addr] [filename] [bytes]\n"
+	"<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n"
 	"    - load binary file 'filename' from 'dev' on 'interface'\n"
 	"      to address 'addr' from ext2 filesystem."
-);
+)
diff --git a/common/cmd_fat.c b/common/cmd_fat.c
index fbe33466fc..a478017448 100644
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -27,7 +27,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	fatload,	7,	0,	do_fat_fsload,
 	"load binary file from a dos filesystem",
-	"<interface> [<dev[:part]>]  <addr> <filename> [bytes [pos]]\n"
+	"<interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]\n"
 	"    - Load binary file 'filename' from 'dev' on 'interface'\n"
 	"      to address 'addr' from dos filesystem.\n"
 	"      'pos' gives the file position to start loading from.\n"
diff --git a/common/cmd_fs.c b/common/cmd_fs.c
index 91a205ac1e..78590d2ef0 100644
--- a/common/cmd_fs.c
+++ b/common/cmd_fs.c
@@ -20,7 +20,8 @@
 #include <command.h>
 #include <fs.h>
 
-int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
 }
@@ -35,9 +36,10 @@ U_BOOT_CMD(
 	"      If 'bytes' is 0 or omitted, the file is read until the end.\n"
 	"      'pos' gives the file byte position to start reading from.\n"
 	"      If 'pos' is 0 or omitted, the file is read from the start."
-);
+)
 
-int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	return do_ls(cmdtp, flag, argc, argv, FS_TYPE_ANY);
 }
@@ -48,4 +50,4 @@ U_BOOT_CMD(
 	"<interface> [<dev[:part]> [directory]]\n"
 	"    - List files in directory 'directory' of partition 'part' on\n"
 	"      device type 'interface' instance 'dev'."
-);
+)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index d714658d7f..3a75f94ea1 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1366,7 +1366,8 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  * Returns zero always.
  */
 #if defined(CONFIG_SYS_I2C)
-int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	int	i;
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
@@ -1425,7 +1426,8 @@ int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  * on error.
  */
 #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
-int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	int		ret = 0;
 	unsigned int	bus_no;
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index c375ef2093..04a6d9b398 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -253,7 +253,7 @@ int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 /* ------------------------------------------------------------------------- */
 
-void __ide_led(uchar led, uchar status)
+__weak void ide_led(uchar led, uchar status)
 {
 #if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
 	static uchar led_buffer;	/* Buffer for current LED status */
@@ -269,9 +269,6 @@ void __ide_led(uchar led, uchar status)
 #endif
 }
 
-void ide_led(uchar led, uchar status)
-	__attribute__ ((weak, alias("__ide_led")));
-
 #ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
 # define DEVICE_LED(x) 0
 # define LED_IDE1 1
@@ -280,7 +277,7 @@ void ide_led(uchar led, uchar status)
 
 /* ------------------------------------------------------------------------- */
 
-inline void __ide_outb(int dev, int port, unsigned char val)
+__weak void ide_outb(int dev, int port, unsigned char val)
 {
 	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
 	      dev, port, val,
@@ -299,10 +296,7 @@ inline void __ide_outb(int dev, int port, unsigned char val)
 #endif
 }
 
-void ide_outb(int dev, int port, unsigned char val)
-	__attribute__ ((weak, alias("__ide_outb")));
-
-inline unsigned char __ide_inb(int dev, int port)
+__weak unsigned char ide_inb(int dev, int port)
 {
 	uchar val;
 
@@ -318,19 +312,6 @@ inline unsigned char __ide_inb(int dev, int port)
 	return val;
 }
 
-unsigned char ide_inb(int dev, int port)
-	__attribute__ ((weak, alias("__ide_inb")));
-
-#ifdef CONFIG_TUNE_PIO
-inline int __ide_set_piomode(int pio_mode)
-{
-	return 0;
-}
-
-inline int ide_set_piomode(int pio_mode)
-	__attribute__ ((weak, alias("__ide_set_piomode")));
-#endif
-
 void ide_init(void)
 {
 	unsigned char c;
@@ -471,23 +452,14 @@ block_dev_desc_t *ide_get_dev(int dev)
 
 /* ------------------------------------------------------------------------- */
 
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-	__attribute__ ((weak, alias("__ide_input_swap_data")));
-
-void ide_input_data(int dev, ulong *sect_buf, int words)
-	__attribute__ ((weak, alias("__ide_input_data")));
-
-void ide_output_data(int dev, const ulong *sect_buf, int words)
-	__attribute__ ((weak, alias("__ide_output_data")));
-
 /* We only need to swap data if we are running on a big endian cpu. */
 #if defined(__LITTLE_ENDIAN)
-void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
 {
 	ide_input_data(dev, sect_buf, words);
 }
 #else
-void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
 {
 	volatile ushort *pbuf =
 		(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
@@ -510,7 +482,7 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
 
 
 #if defined(CONFIG_IDE_SWAP_IO)
-void __ide_output_data(int dev, const ulong *sect_buf, int words)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
@@ -525,7 +497,7 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words)
 	}
 }
 #else  /* ! CONFIG_IDE_SWAP_IO */
-void __ide_output_data(int dev, const ulong *sect_buf, int words)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
 {
 #if defined(CONFIG_IDE_AHB)
 	ide_write_data(dev, sect_buf, words);
@@ -536,7 +508,7 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words)
 #endif /* CONFIG_IDE_SWAP_IO */
 
 #if defined(CONFIG_IDE_SWAP_IO)
-void __ide_input_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
@@ -554,7 +526,7 @@ void __ide_input_data(int dev, ulong *sect_buf, int words)
 	}
 }
 #else  /* ! CONFIG_IDE_SWAP_IO */
-void __ide_input_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
 {
 #if defined(CONFIG_IDE_AHB)
 	ide_read_data(dev, sect_buf, words);
@@ -575,14 +547,6 @@ static void ide_ident(block_dev_desc_t *dev_desc)
 #ifdef CONFIG_ATAPI
 	int retries = 0;
 #endif
-
-#ifdef CONFIG_TUNE_PIO
-	int pio_mode;
-#endif
-
-#if 0
-	int mode, cycle_time;
-#endif
 	int device;
 
 	device = dev_desc->dev;
@@ -691,72 +655,6 @@ static void ide_ident(block_dev_desc_t *dev_desc)
 	else
 		dev_desc->removable = 0;
 
-#ifdef CONFIG_TUNE_PIO
-	/* Mode 0 - 2 only, are directly determined by word 51. */
-	pio_mode = iop.tPIO;
-	if (pio_mode > 2) {
-		printf("WARNING: Invalid PIO (word 51 = %d).\n", pio_mode);
-		/* Force it to dead slow, and hope for the best... */
-		pio_mode = 0;
-	}
-
-	/* Any CompactFlash Storage Card that supports PIO mode 3 or above
-	 * shall set bit 1 of word 53 to one and support the fields contained
-	 * in words 64 through 70.
-	 */
-	if (iop.field_valid & 0x02) {
-		/*
-		 * Mode 3 and above are possible.  Check in order from slow
-		 * to fast, so we wind up with the highest mode allowed.
-		 */
-		if (iop.eide_pio_modes & 0x01)
-			pio_mode = 3;
-		if (iop.eide_pio_modes & 0x02)
-			pio_mode = 4;
-		if (ata_id_is_cfa((u16 *)&iop)) {
-			if ((iop.cf_advanced_caps & 0x07) == 0x01)
-				pio_mode = 5;
-			if ((iop.cf_advanced_caps & 0x07) == 0x02)
-				pio_mode = 6;
-		}
-	}
-
-	/* System-specific, depends on bus speeds, etc. */
-	ide_set_piomode(pio_mode);
-#endif /* CONFIG_TUNE_PIO */
-
-#if 0
-	/*
-	 * Drive PIO mode autoselection
-	 */
-	mode = iop.tPIO;
-
-	printf("tPIO = 0x%02x = %d\n", mode, mode);
-	if (mode > 2) {		/* 2 is maximum allowed tPIO value */
-		mode = 2;
-		debug("Override tPIO -> 2\n");
-	}
-	if (iop.field_valid & 2) {	/* drive implements ATA2? */
-		debug("Drive implements ATA2\n");
-		if (iop.capability & 8) {	/* drive supports use_iordy? */
-			cycle_time = iop.eide_pio_iordy;
-		} else {
-			cycle_time = iop.eide_pio;
-		}
-		debug("cycle time = %d\n", cycle_time);
-		mode = 4;
-		if (cycle_time > 120)
-			mode = 3;	/* 120 ns for PIO mode 4 */
-		if (cycle_time > 180)
-			mode = 2;	/* 180 ns for PIO mode 3 */
-		if (cycle_time > 240)
-			mode = 1;	/* 240 ns for PIO mode 4 */
-		if (cycle_time > 383)
-			mode = 0;	/* 383 ns for PIO mode 4 */
-	}
-	printf("PIO mode to use: PIO %d\n", mode);
-#endif /* 0 */
-
 #ifdef CONFIG_ATAPI
 	if (dev_desc->if_type == IF_TYPE_ATAPI) {
 		atapi_inquiry(dev_desc);
@@ -1122,17 +1020,10 @@ int ide_device_present(int dev)
  * ATAPI Support
  */
 
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-	__attribute__ ((weak, alias("__ide_input_data_shorts")));
-
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-	__attribute__ ((weak, alias("__ide_output_data_shorts")));
-
-
 #if defined(CONFIG_IDE_SWAP_IO)
 /* since ATAPI may use commands with not 4 bytes alligned length
  * we have our own transfer functions, 2 bytes alligned */
-void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
@@ -1149,7 +1040,7 @@ void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 	}
 }
 
-void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
@@ -1167,12 +1058,12 @@ void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 }
 
 #else  /* ! CONFIG_IDE_SWAP_IO */
-void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
 	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
 }
 
-void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
 	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
 }
diff --git a/common/cmd_log.c b/common/cmd_log.c
index 38d0f5edfd..873ee40371 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -33,8 +33,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Local prototypes */
-static void logbuff_putc(const char c);
-static void logbuff_puts(const char *s);
+static void logbuff_putc(struct stdio_dev *dev, const char c);
+static void logbuff_puts(struct stdio_dev *dev, const char *s);
 static int logbuff_printk(const char *line);
 
 static char buf[1024];
@@ -143,7 +143,7 @@ int drv_logbuff_init(void)
 	return (rc == 0) ? 1 : rc;
 }
 
-static void logbuff_putc(const char c)
+static void logbuff_putc(struct stdio_dev *dev, const char c)
 {
 	char buf[2];
 	buf[0] = c;
@@ -151,7 +151,7 @@ static void logbuff_putc(const char c)
 	logbuff_printk(buf);
 }
 
-static void logbuff_puts(const char *s)
+static void logbuff_puts(struct stdio_dev *dev, const char *s)
 {
 	logbuff_printk (s);
 }
@@ -181,6 +181,7 @@ void logbuff_log(char *msg)
  */
 int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	struct stdio_dev *sdev = NULL;
 	char *s;
 	unsigned long i, start, size;
 
@@ -188,7 +189,7 @@ int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		/* Log concatenation of all arguments separated by spaces */
 		for (i = 2; i < argc; i++) {
 			logbuff_printk(argv[i]);
-			logbuff_putc((i < argc - 1) ? ' ' : '\n');
+			logbuff_putc(sdev, (i < argc - 1) ? ' ' : '\n');
 		}
 		return 0;
 	}
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index b82a7ce612..7c4a57aa56 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -160,10 +160,10 @@ static void dump_reg(
 
 		mask_in_place = pdesc->mask << pdesc->lo;
 
-		printf("  (%04hx:%04hx) %u.",
-			mask_in_place,
-			regval & mask_in_place,
-			prd->regno);
+		printf("  (%04hx:%04x) %u.",
+		       mask_in_place,
+		       regval & mask_in_place,
+		       prd->regno);
 
 		if (special_field(prd->regno, pdesc, regval)) {
 		}
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index e6c33956e7..855808c3e4 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -950,11 +950,15 @@ sep_err:
 
 #ifdef CONFIG_CMD_IMPORTENV
 /*
- * env import [-d] [-t | -b | -c] addr [size]
+ * env import [-d] [-t [-r] | -b | -c] addr [size]
  *	-d:	delete existing environment before importing;
  *		otherwise overwrite / append to existion definitions
  *	-t:	assume text format; either "size" must be given or the
  *		text data must be '\0' terminated
+ *	-r:	handle CRLF like LF, that means exported variables with
+ *		a content which ends with \r won't get imported. Used
+ *		to import text files created with editors which are using CRLF
+ *		for line endings. Only effective in addition to -t.
  *	-b:	assume binary format ('\0' separated, "\0\0" terminated)
  *	-c:	assume checksum protected environment format
  *	addr:	memory address to read from
@@ -970,6 +974,7 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
 	int	chk = 0;
 	int	fmt = 0;
 	int	del = 0;
+	int	crlf_is_lf = 0;
 	size_t	size;
 
 	cmd = *argv;
@@ -994,6 +999,9 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
 					goto sep_err;
 				sep = '\n';
 				break;
+			case 'r':		/* handle CRLF like LF */
+				crlf_is_lf = 1;
+				break;
 			case 'd':
 				del = 1;
 				break;
@@ -1009,6 +1017,9 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
 	if (!fmt)
 		printf("## Warning: defaulting to text format\n");
 
+	if (sep != '\n' && crlf_is_lf )
+		crlf_is_lf = 0;
+
 	addr = simple_strtoul(argv[0], NULL, 16);
 	ptr = map_sysmem(addr, 0);
 
@@ -1050,8 +1061,8 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
 		ptr = (char *)ep->data;
 	}
 
-	if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR, 0,
-		      NULL) == 0) {
+	if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR,
+			crlf_is_lf, 0, NULL) == 0) {
 		error("Environment import failed: errno = %d\n", errno);
 		return 1;
 	}
@@ -1180,7 +1191,7 @@ static char env_help_text[] =
 #endif
 #endif
 #if defined(CONFIG_CMD_IMPORTENV)
-	"env import [-d] [-t | -b | -c] addr [size] - import environment\n"
+	"env import [-d] [-t [-r] | -b | -c] addr [size] - import environment\n"
 #endif
 	"env print [-a | name ...] - print environment\n"
 #if defined(CONFIG_CMD_RUN)
diff --git a/common/cmd_part.c b/common/cmd_part.c
index c84bc27b40..39e8666b77 100644
--- a/common/cmd_part.c
+++ b/common/cmd_part.c
@@ -26,7 +26,7 @@
 #error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled
 #endif
 
-int do_part_uuid(int argc, char * const argv[])
+static int do_part_uuid(int argc, char * const argv[])
 {
 	int part;
 	block_dev_desc_t *dev_desc;
@@ -49,7 +49,7 @@ int do_part_uuid(int argc, char * const argv[])
 	return 0;
 }
 
-int do_part_list(int argc, char * const argv[])
+static int do_part_list(int argc, char * const argv[])
 {
 	int ret;
 	block_dev_desc_t *desc;
@@ -66,7 +66,7 @@ int do_part_list(int argc, char * const argv[])
 	return 0;
 }
 
-int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	if (argc < 2)
 		return CMD_RET_USAGE;
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
index 348332874b..ba48692e86 100644
--- a/common/cmd_pxe.c
+++ b/common/cmd_pxe.c
@@ -1562,7 +1562,7 @@ static cmd_tbl_t cmd_pxe_sub[] = {
 	U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "")
 };
 
-int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	cmd_tbl_t *cp;
 
@@ -1596,7 +1596,7 @@ U_BOOT_CMD(
  *
  * Returns 0 on success, 1 on error.
  */
-int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned long pxefile_addr_r;
 	struct pxe_menu *cfg;
diff --git a/common/cmd_source.c b/common/cmd_source.c
index f3e9e605e1..6881bc9ddd 100644
--- a/common/cmd_source.c
+++ b/common/cmd_source.c
@@ -142,8 +142,7 @@ source (ulong addr, const char *fit_uname)
 
 /**************************************************/
 #if defined(CONFIG_CMD_SOURCE)
-int
-do_source (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_source(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong addr;
 	int rcode;
diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c
index 7c4d950e96..3c37c93f10 100644
--- a/common/cmd_ubi.c
+++ b/common/cmd_ubi.c
@@ -287,7 +287,7 @@ out_err:
 	return err;
 }
 
-int ubi_volume_continue_write(char *volume, void *buf, size_t size)
+static int ubi_volume_continue_write(char *volume, void *buf, size_t size)
 {
 	int err = 1;
 	struct ubi_volume *vol;
diff --git a/common/cmd_ubifs.c b/common/cmd_ubifs.c
index fdc8bfe46a..19c8a43ce4 100644
--- a/common/cmd_ubifs.c
+++ b/common/cmd_ubifs.c
@@ -21,7 +21,8 @@
 static int ubifs_initialized;
 static int ubifs_mounted;
 
-int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	char *vol_name;
 	int ret;
@@ -65,7 +66,8 @@ void cmd_ubifs_umount(void)
 	ubifs_initialized = 0;
 }
 
-int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	if (argc != 1)
 		return CMD_RET_USAGE;
@@ -80,7 +82,8 @@ int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
 {
 	char *filename = "/";
 	int ret;
@@ -103,7 +106,8 @@ int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return ret;
 }
 
-int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[])
 {
 	char *filename;
 	char *endp;
diff --git a/common/console.c b/common/console.c
index 5453726f69..898da3935e 100644
--- a/common/console.c
+++ b/common/console.c
@@ -109,7 +109,7 @@ static int console_setfile(int file, struct stdio_dev * dev)
 	case stderr:
 		/* Start new device */
 		if (dev->start) {
-			error = dev->start();
+			error = dev->start(dev);
 			/* If it's not started dont use it */
 			if (error < 0)
 				break;
@@ -159,7 +159,7 @@ static int console_getc(int file)
 	unsigned char ret;
 
 	/* This is never called with testcdev == NULL */
-	ret = tstcdev->getc();
+	ret = tstcdev->getc(tstcdev);
 	tstcdev = NULL;
 	return ret;
 }
@@ -173,7 +173,7 @@ static int console_tstc(int file)
 	for (i = 0; i < cd_count[file]; i++) {
 		dev = console_devices[file][i];
 		if (dev->tstc != NULL) {
-			ret = dev->tstc();
+			ret = dev->tstc(dev);
 			if (ret > 0) {
 				tstcdev = dev;
 				disable_ctrlc(0);
@@ -194,7 +194,7 @@ static void console_putc(int file, const char c)
 	for (i = 0; i < cd_count[file]; i++) {
 		dev = console_devices[file][i];
 		if (dev->putc != NULL)
-			dev->putc(c);
+			dev->putc(dev, c);
 	}
 }
 
@@ -206,7 +206,7 @@ static void console_puts(int file, const char *s)
 	for (i = 0; i < cd_count[file]; i++) {
 		dev = console_devices[file][i];
 		if (dev->puts != NULL)
-			dev->puts(s);
+			dev->puts(dev, s);
 	}
 }
 
@@ -222,22 +222,22 @@ static inline void console_doenv(int file, struct stdio_dev *dev)
 #else
 static inline int console_getc(int file)
 {
-	return stdio_devices[file]->getc();
+	return stdio_devices[file]->getc(stdio_devices[file]);
 }
 
 static inline int console_tstc(int file)
 {
-	return stdio_devices[file]->tstc();
+	return stdio_devices[file]->tstc(stdio_devices[file]);
 }
 
 static inline void console_putc(int file, const char c)
 {
-	stdio_devices[file]->putc(c);
+	stdio_devices[file]->putc(stdio_devices[file], c);
 }
 
 static inline void console_puts(int file, const char *s)
 {
-	stdio_devices[file]->puts(s);
+	stdio_devices[file]->puts(stdio_devices[file], s);
 }
 
 static inline void console_printdevs(int file)
@@ -417,7 +417,7 @@ static inline void print_pre_console_buffer(void) {}
 void putc(const char c)
 {
 #ifdef CONFIG_SANDBOX
-	if (!gd) {
+	if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
 		os_putc(c);
 		return;
 	}
@@ -447,7 +447,7 @@ void putc(const char c)
 void puts(const char *s)
 {
 #ifdef CONFIG_SANDBOX
-	if (!gd) {
+	if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
 		os_puts(s);
 		return;
 	}
@@ -504,7 +504,7 @@ int vprintf(const char *fmt, va_list args)
 	uint i;
 	char printbuffer[CONFIG_SYS_PBSIZE];
 
-#ifndef CONFIG_PRE_CONSOLE_BUFFER
+#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX)
 	if (!gd->have_console)
 		return 0;
 #endif
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 3c70d5dede..f9873393c1 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1,5 +1,9 @@
 #include <common.h>
 
+#ifdef CONFIG_SANDBOX
+#define DEBUG
+#endif
+
 #if 0	/* Moved to malloc.h */
 /* ---------- To make a malloc.h, start cutting here ------------ */
 
@@ -220,7 +224,7 @@
 
 */
 
-
+
 
 /* Preliminaries */
 
@@ -930,6 +934,8 @@ struct mallinfo mALLINFo();
 #endif	/* 0 */			/* Moved to malloc.h */
 
 #include <malloc.h>
+#include <asm/io.h>
+
 #ifdef DEBUG
 #if __STD_C
 static void malloc_update_mallinfo (void);
@@ -1132,7 +1138,7 @@ gAllocatedSize))
 
 #endif
 
-
+
 
 /*
   Type declarations
@@ -1272,7 +1278,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
        serviced via calls to mmap, and then later released via munmap.
 
 */
-
+
 /*  sizes, alignments */
 
 #define SIZE_SZ                (sizeof(INTERNAL_SIZE_T))
@@ -1297,7 +1303,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 #define aligned_OK(m)    (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0)
 
 
-
+
 
 /*
   Physical chunk operations
@@ -1332,7 +1338,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 #define chunk_at_offset(p, s)  ((mchunkptr)(((char*)(p)) + (s)))
 
 
-
+
 
 /*
   Dealing with use bits
@@ -1371,7 +1377,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE))
 
 
-
+
 
 /*
   Dealing with size fields
@@ -1394,7 +1400,7 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 #define set_foot(p, s)   (((mchunkptr)((char*)(p) + (s)))->prev_size = (s))
 
 
-
+
 
 
 /*
@@ -1566,7 +1572,7 @@ void mem_malloc_init(ulong start, ulong size)
 
 #define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH)
 
-
+
 
 /*
     To help compensate for the large number of bins, a one-level index
@@ -1590,7 +1596,7 @@ void mem_malloc_init(ulong start, ulong size)
 #define clear_binblock(ii)  (binblocks_w = (mbinptr)(binblocks_r & ~(idx2binblock(ii))))
 
 
-
+
 
 
 /*  Other static bookkeeping data */
@@ -1628,7 +1634,7 @@ static unsigned int max_n_mmaps = 0;
 static unsigned long max_mmapped_mem = 0;
 #endif
 
-
+
 
 /*
   Debugging support
@@ -1769,7 +1775,7 @@ static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s;
 #define check_malloced_chunk(P,N)
 #endif
 
-
+
 
 /*
   Macro-based internal utilities
@@ -1841,7 +1847,7 @@ static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s;
   (last_remainder->fd = last_remainder->bk = last_remainder)
 
 
-
+
 
 
 /* Routines dealing with mmap(). */
@@ -1972,7 +1978,7 @@ static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size;
 #endif /* HAVE_MMAP */
 
 
-
+
 
 /*
   Extend the top-most chunk by obtaining memory from system.
@@ -2089,7 +2095,7 @@ static void malloc_extend_top(nb) INTERNAL_SIZE_T nb;
 }
 
 
-
+
 
 /* Main public routines */
 
@@ -2174,6 +2180,20 @@ Void_t* mALLOc(bytes) size_t bytes;
 
   INTERNAL_SIZE_T nb;
 
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		ulong new_ptr;
+		void *ptr;
+
+		new_ptr = gd->malloc_ptr + bytes;
+		if (new_ptr > gd->malloc_limit)
+			panic("Out of pre-reloc memory");
+		ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
+		gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+		return ptr;
+	}
+#endif
+
   /* check if mem_malloc_init() was run */
   if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) {
     /* not initialized yet */
@@ -2396,7 +2416,7 @@ Void_t* mALLOc(bytes) size_t bytes;
 }
 
 
-
+
 
 /*
 
@@ -2437,6 +2457,12 @@ void fREe(mem) Void_t* mem;
   mchunkptr fwd;       /* misc temp for linking */
   int       islr;      /* track whether merging with last_remainder */
 
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	/* free() is a no-op - all the memory will be freed on relocation */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return;
+#endif
+
   if (mem == NULL)                              /* free(0) has no effect */
     return;
 
@@ -2513,7 +2539,7 @@ void fREe(mem) Void_t* mem;
 }
 
 
-
+
 
 
 /*
@@ -2588,6 +2614,13 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes;
   /* realloc of null is supposed to be same as malloc */
   if (oldmem == NULL) return mALLOc(bytes);
 
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		/* This is harder to support and should not be needed */
+		panic("pre-reloc realloc() is not supported");
+	}
+#endif
+
   newp    = oldp    = mem2chunk(oldmem);
   newsize = oldsize = chunksize(oldp);
 
@@ -2750,7 +2783,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes;
 }
 
 
-
+
 
 /*
 
@@ -2868,7 +2901,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes;
 
 }
 
-
+
 
 
 /*
@@ -2933,6 +2966,12 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size;
     return NULL;
   else
   {
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		MALLOC_ZERO(mem, sz);
+		return mem;
+	}
+#endif
     p = mem2chunk(mem);
 
     /* Two optional cases in which clearing not necessary */
@@ -2975,7 +3014,7 @@ void cfree(mem) Void_t *mem;
 }
 #endif
 
-
+
 
 /*
 
@@ -3056,7 +3095,7 @@ int malloc_trim(pad) size_t pad;
   }
 }
 
-
+
 
 /*
   malloc_usable_size:
@@ -3092,7 +3131,7 @@ size_t malloc_usable_size(mem) Void_t* mem;
 }
 
 
-
+
 
 /* Utility to update current_mallinfo for malloc_stats and mallinfo() */
 
@@ -3136,7 +3175,7 @@ static void malloc_update_mallinfo()
 }
 #endif	/* DEBUG */
 
-
+
 
 /*
 
@@ -3183,7 +3222,7 @@ struct mallinfo mALLINFo()
 #endif	/* DEBUG */
 
 
-
+
 
 /*
   mallopt:
diff --git a/common/env_common.c b/common/env_common.c
index cd7b4cd1df..af59c72e1f 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -27,12 +27,10 @@ struct hsearch_data env_htab = {
 	.change_ok = env_flags_validate,
 };
 
-static uchar __env_get_char_spec(int index)
+__weak uchar env_get_char_spec(int index)
 {
 	return *((uchar *)(gd->env_addr + index));
 }
-uchar env_get_char_spec(int)
-	__attribute__((weak, alias("__env_get_char_spec")));
 
 static uchar env_get_char_init(int index)
 {
@@ -120,7 +118,7 @@ void set_default_env(const char *s)
 	}
 
 	if (himport_r(&env_htab, (char *)default_environment,
-			sizeof(default_environment), '\0', flags,
+			sizeof(default_environment), '\0', flags, 0,
 			0, NULL) == 0)
 		error("Environment import failed: errno = %d\n", errno);
 
@@ -137,7 +135,7 @@ int set_default_vars(int nvars, char * const vars[])
 	 */
 	return himport_r(&env_htab, (const char *)default_environment,
 				sizeof(default_environment), '\0',
-				H_NOCLEAR | H_INTERACTIVE, nvars, vars);
+				H_NOCLEAR | H_INTERACTIVE, 0, nvars, vars);
 }
 
 #ifdef CONFIG_ENV_AES
@@ -214,7 +212,7 @@ int env_import(const char *buf, int check)
 		return ret;
 	}
 
-	if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0,
+	if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0,
 			0, NULL)) {
 		gd->flags |= GD_FLG_ENV_READY;
 		return 1;
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 9fc7481fd8..db6e395562 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -450,7 +450,7 @@ __weak int ft_verify_fdt(void *fdt)
 	return 1;
 }
 
-__weak int arch_fixup_memory_node(void *blob)
+__weak int arch_fixup_fdt(void *blob)
 {
 	return 0;
 }
@@ -467,7 +467,10 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 		puts(" - must RESET the board to recover.\n");
 		return -1;
 	}
-	arch_fixup_memory_node(blob);
+	if (arch_fixup_fdt(blob) < 0) {
+		puts("ERROR: arch specific fdt fixup failed");
+		return -1;
+	}
 	if (IMAGE_OF_BOARD_SETUP)
 		ft_board_setup(blob, gd->bd);
 	fdt_fixup_ethernet(blob);
@@ -492,7 +495,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,
 	if (!ft_verify_fdt(blob))
 		return -1;
 
-#ifdef CONFIG_SOC_K2HK
+#if defined(CONFIG_SOC_KEYSTONE)
 	if (IMAGE_OF_BOARD_SETUP)
 		ft_board_setup_ex(blob, gd->bd);
 #endif
diff --git a/common/lcd.c b/common/lcd.c
index 19b86b7c55..feb913a720 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -214,6 +214,11 @@ static inline void console_newline(void)
 
 /*----------------------------------------------------------------------*/
 
+static void lcd_stub_putc(struct stdio_dev *dev, const char c)
+{
+	lcd_putc(c);
+}
+
 void lcd_putc(const char c)
 {
 	if (!lcd_is_enabled) {
@@ -253,6 +258,11 @@ void lcd_putc(const char c)
 
 /*----------------------------------------------------------------------*/
 
+static void lcd_stub_puts(struct stdio_dev *dev, const char *s)
+{
+	lcd_puts(s);
+}
+
 void lcd_puts(const char *s)
 {
 	if (!lcd_is_enabled) {
@@ -426,8 +436,8 @@ int drv_lcd_init(void)
 	strcpy(lcddev.name, "lcd");
 	lcddev.ext   = 0;			/* No extensions */
 	lcddev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
-	lcddev.putc  = lcd_putc;		/* 'putc' function */
-	lcddev.puts  = lcd_puts;		/* 'puts' function */
+	lcddev.putc  = lcd_stub_putc;		/* 'putc' function */
+	lcddev.puts  = lcd_stub_puts;		/* 'puts' function */
 
 	rc = stdio_register(&lcddev);
 
diff --git a/common/main.c b/common/main.c
index 32618f139f..2979fbed63 100644
--- a/common/main.c
+++ b/common/main.c
@@ -17,8 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * Board-specific Platform code can reimplement show_boot_progress () if needed
  */
-void inline __show_boot_progress (int val) {}
-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
+__weak void show_boot_progress(int val) {}
 
 static void modem_init(void)
 {
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 062461b2b6..9b200bc4d5 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -44,7 +44,7 @@ void spl_nand_load_image(void)
 
 		/* load linux */
 		nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
-			CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+			sizeof(*header), (void *)header);
 		spl_parse_image_header(header);
 		if (header->ih_os == IH_OS_LINUX) {
 			/* happy - was a linux */
@@ -62,13 +62,13 @@ void spl_nand_load_image(void)
 #endif
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET,
-		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+		sizeof(*header), (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
 		(void *)spl_image.load_addr);
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
-		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+		sizeof(*header), (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
 		(void *)spl_image.load_addr);
diff --git a/common/splash.c b/common/splash.c
index 18885f1bfe..144fb10ddd 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -23,15 +23,11 @@
 #include <common.h>
 #include <splash.h>
 
-int __splash_screen_prepare(void)
+__weak int splash_screen_prepare(void)
 {
 	return 0;
 }
 
-int splash_screen_prepare(void)
-	__attribute__ ((weak, alias("__splash_screen_prepare")));
-
-
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
 void splash_get_pos(int *x, int *y)
 {
diff --git a/common/stdio.c b/common/stdio.c
index 844f98c184..692ca7f1cd 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -11,6 +11,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <errno.h>
 #include <stdarg.h>
 #include <malloc.h>
 #include <stdio_dev.h>
@@ -35,23 +36,43 @@ char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
 
 
 #ifdef CONFIG_SYS_DEVICE_NULLDEV
-void nulldev_putc(const char c)
+void nulldev_putc(struct stdio_dev *dev, const char c)
 {
 	/* nulldev is empty! */
 }
 
-void nulldev_puts(const char *s)
+void nulldev_puts(struct stdio_dev *dev, const char *s)
 {
 	/* nulldev is empty! */
 }
 
-int nulldev_input(void)
+int nulldev_input(struct stdio_dev *dev)
 {
 	/* nulldev is empty! */
 	return 0;
 }
 #endif
 
+void stdio_serial_putc(struct stdio_dev *dev, const char c)
+{
+	serial_putc(c);
+}
+
+void stdio_serial_puts(struct stdio_dev *dev, const char *s)
+{
+	serial_puts(s);
+}
+
+int stdio_serial_getc(struct stdio_dev *dev)
+{
+	return serial_getc();
+}
+
+int stdio_serial_tstc(struct stdio_dev *dev)
+{
+	return serial_tstc();
+}
+
 /**************************************************************************
  * SYSTEM DRIVERS
  **************************************************************************
@@ -65,10 +86,10 @@ static void drv_system_init (void)
 
 	strcpy (dev.name, "serial");
 	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-	dev.putc = serial_putc;
-	dev.puts = serial_puts;
-	dev.getc = serial_getc;
-	dev.tstc = serial_tstc;
+	dev.putc = stdio_serial_putc;
+	dev.puts = stdio_serial_puts;
+	dev.getc = stdio_serial_getc;
+	dev.tstc = stdio_serial_tstc;
 	stdio_register (&dev);
 
 #ifdef CONFIG_SYS_DEVICE_NULLDEV
@@ -128,32 +149,35 @@ struct stdio_dev* stdio_clone(struct stdio_dev *dev)
 	return _dev;
 }
 
-int stdio_register (struct stdio_dev * dev)
+int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp)
 {
 	struct stdio_dev *_dev;
 
 	_dev = stdio_clone(dev);
 	if(!_dev)
-		return -1;
+		return -ENODEV;
 	list_add_tail(&(_dev->list), &(devs.list));
+	if (devp)
+		*devp = _dev;
+
 	return 0;
 }
 
+int stdio_register(struct stdio_dev *dev)
+{
+	return stdio_register_dev(dev, NULL);
+}
+
 /* deregister the device "devname".
  * returns 0 if success, -1 if device is assigned and 1 if devname not found
  */
 #ifdef	CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(const char *devname)
+int stdio_deregister_dev(struct stdio_dev *dev)
 {
 	int l;
 	struct list_head *pos;
-	struct stdio_dev *dev;
 	char temp_names[3][16];
 
-	dev = stdio_get_by_name(devname);
-
-	if(!dev) /* device not found */
-		return -1;
 	/* get stdio devices (ListRemoveItem changes the dev list) */
 	for (l=0 ; l< MAX_FILES; l++) {
 		if (stdio_devices[l] == dev) {
@@ -177,6 +201,18 @@ int stdio_deregister(const char *devname)
 	}
 	return 0;
 }
+
+int stdio_deregister(const char *devname)
+{
+	struct stdio_dev *dev;
+
+	dev = stdio_get_by_name(devname);
+
+	if (!dev) /* device not found */
+		return -ENODEV;
+
+	return stdio_deregister_dev(dev);
+}
 #endif	/* CONFIG_SYS_STDIO_DEREGISTER */
 
 int stdio_init (void)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 0b77c16c5f..c34fd5c786 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -360,7 +360,7 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev)
 }
 
 /* test if a character is in the queue */
-static int usb_kbd_testc(void)
+static int usb_kbd_testc(struct stdio_dev *sdev)
 {
 	struct stdio_dev *dev;
 	struct usb_device *usb_kbd_dev;
@@ -386,7 +386,7 @@ static int usb_kbd_testc(void)
 }
 
 /* gets the character from the queue */
-static int usb_kbd_getc(void)
+static int usb_kbd_getc(struct stdio_dev *sdev)
 {
 	struct stdio_dev *dev;
 	struct usb_device *usb_kbd_dev;
@@ -522,8 +522,6 @@ int drv_usb_kbd_init(void)
 		memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev));
 		strcpy(usb_kbd_dev.name, DEVNAME);
 		usb_kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-		usb_kbd_dev.putc = NULL;
-		usb_kbd_dev.puts = NULL;
 		usb_kbd_dev.getc = usb_kbd_getc;
 		usb_kbd_dev.tstc = usb_kbd_testc;
 		usb_kbd_dev.priv = (void *)dev;
diff --git a/disk/part.c b/disk/part.c
index baceb19c60..ecc5e7e0bf 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -333,7 +333,7 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
 
 #endif /* any CONFIG_..._PARTITION */
 
-void print_part (block_dev_desc_t * dev_desc)
+void print_part(block_dev_desc_t * dev_desc)
 {
 
 		switch (dev_desc->part_type) {
@@ -381,8 +381,8 @@ void print_part (block_dev_desc_t * dev_desc)
 
 #endif /* HAVE_BLOCK_DEVICE */
 
-int get_partition_info(block_dev_desc_t *dev_desc, int part
-					, disk_partition_t *info)
+int get_partition_info(block_dev_desc_t *dev_desc, int part,
+		       disk_partition_t *info)
 {
 #ifdef HAVE_BLOCK_DEVICE
 
@@ -511,7 +511,7 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str,
 	disk_partition_t tmpinfo;
 
 	/*
-	 * Special-case a psuedo block device "hostfs", to allow access to the
+	 * Special-case a pseudo block device "hostfs", to allow access to the
 	 * host's own filesystem.
 	 */
 	if (0 == strcmp(ifname, "hostfs")) {
diff --git a/doc/README.nand b/doc/README.nand
index 70cf768d23..e29188f1ec 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -89,6 +89,10 @@ Commands:
 
 Configuration Options:
 
+   CONFIG_SYS_NAND_U_BOOT_OFFS
+	NAND Offset from where SPL will read u-boot image. This is the starting
+	address of u-boot MTD partition in NAND.
+
    CONFIG_CMD_NAND
       Enables NAND support and commmands.
 
@@ -226,6 +230,14 @@ Platform specific options
 	detection. However ECC calculation on such plaforms would still be
 	done by GPMC controller.
 
+   CONFIG_SPL_NAND_AM33XX_BCH
+	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+        hardware ECC correction. This is useful for platforms which have ELM
+	hardware engine and use NAND boot mode.
+	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+        SPL-NAND driver with software ECC correction support.
+
    CONFIG_NAND_OMAP_ECCSCHEME
 	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
 	It can take following values:
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index 22c3fcb6ef..f9b68beb6f 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -95,26 +95,37 @@ are provided in test/dm. To run them, try:
 You should see something like this:
 
     <...U-Boot banner...>
-    Running 12 driver model tests
+    Running 21 driver model tests
     Test: dm_test_autobind
     Test: dm_test_autoprobe
+    Test: dm_test_bus_children
+    Device 'd-test': seq 3 is in use by 'b-test'
+    Device 'c-test@0': seq 0 is in use by 'a-test'
+    Device 'c-test@1': seq 1 is in use by 'd-test'
+    Test: dm_test_bus_children_funcs
+    Test: dm_test_bus_parent_data
+    Test: dm_test_bus_parent_ops
     Test: dm_test_children
     Test: dm_test_fdt
+    Device 'd-test': seq 3 is in use by 'b-test'
+    Test: dm_test_fdt_offset
+    Test: dm_test_fdt_pre_reloc
+    Test: dm_test_fdt_uclass_seq
+    Device 'd-test': seq 3 is in use by 'b-test'
+    Device 'a-test': seq 0 is in use by 'd-test'
     Test: dm_test_gpio
     sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
     Test: dm_test_leak
-    Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
-    Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
     Test: dm_test_lifecycle
     Test: dm_test_operations
     Test: dm_test_ordering
     Test: dm_test_platdata
+    Test: dm_test_pre_reloc
     Test: dm_test_remove
     Test: dm_test_uclass
+    Test: dm_test_uclass_before_ready
     Failures: 0
 
-(You can add '#define DEBUG' as suggested to check for memory leaks)
-
 
 What is going on?
 -----------------
@@ -341,6 +352,145 @@ numbering comes from include/dm/uclass.h. To add a new uclass, add to the
 end of the enum there, then declare your uclass as above.
 
 
+Device Sequence Numbers
+-----------------------
+
+U-Boot numbers devices from 0 in many situations, such as in the command
+line for I2C and SPI buses, and the device names for serial ports (serial0,
+serial1, ...). Driver model supports this numbering and permits devices
+to be locating by their 'sequence'.
+
+Sequence numbers start from 0 but gaps are permitted. For example, a board
+may have I2C buses 0, 1, 4, 5 but no 2 or 3. The choice of how devices are
+numbered is up to a particular board, and may be set by the SoC in some
+cases. While it might be tempting to automatically renumber the devices
+where there are gaps in the sequence, this can lead to confusion and is
+not the way that U-Boot works.
+
+Each device can request a sequence number. If none is required then the
+device will be automatically allocated the next available sequence number.
+
+To specify the sequence number in the device tree an alias is typically
+used.
+
+aliases {
+	serial2 = "/serial@22230000";
+};
+
+This indicates that in the uclass called "serial", the named node
+("/serial@22230000") will be given sequence number 2. Any command or driver
+which requests serial device 2 will obtain this device.
+
+Some devices represent buses where the devices on the bus are numbered or
+addressed. For example, SPI typically numbers its slaves from 0, and I2C
+uses a 7-bit address. In these cases the 'reg' property of the subnode is
+used, for example:
+
+{
+	aliases {
+		spi2 = "/spi@22300000";
+	};
+
+	spi@22300000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-flash@0 {
+			reg = <0>;
+			...
+		}
+		eeprom@1 {
+			reg = <1>;
+		};
+	};
+
+In this case we have a SPI bus with two slaves at 0 and 1. The SPI bus
+itself is numbered 2. So we might access the SPI flash with:
+
+	sf probe 2:0
+
+and the eeprom with
+
+	sspi 2:1 32 ef
+
+These commands simply need to look up the 2nd device in the SPI uclass to
+find the right SPI bus. Then, they look at the children of that bus for the
+right sequence number (0 or 1 in this case).
+
+Typically the alias method is used for top-level nodes and the 'reg' method
+is used only for buses.
+
+Device sequence numbers are resolved when a device is probed. Before then
+the sequence number is only a request which may or may not be honoured,
+depending on what other devices have been probed. However the numbering is
+entirely under the control of the board author so a conflict is generally
+an error.
+
+
+Bus Drivers
+-----------
+
+A common use of driver model is to implement a bus, a device which provides
+access to other devices. Example of buses include SPI and I2C. Typically
+the bus provides some sort of transport or translation that makes it
+possible to talk to the devices on the bus.
+
+Driver model provides a few useful features to help with implementing
+buses. Firstly, a bus can request that its children store some 'parent
+data' which can be used to keep track of child state. Secondly, the bus can
+define methods which are called when a child is probed or removed. This is
+similar to the methods the uclass driver provides.
+
+Here an explanation of how a bus fits with a uclass may be useful. Consider
+a USB bus with several devices attached to it, each from a different (made
+up) uclass:
+
+   xhci_usb (UCLASS_USB)
+      eth (UCLASS_ETHERNET)
+      camera (UCLASS_CAMERA)
+      flash (UCLASS_FLASH_STORAGE)
+
+Each of the devices is connected to a different address on the USB bus.
+The bus device wants to store this address and some other information such
+as the bus speed for each device.
+
+To achieve this, the bus device can use dev->parent_priv in each of its
+three children. This can be auto-allocated if the bus driver has a non-zero
+value for per_child_auto_alloc_size. If not, then the bus device can
+allocate the space itself before the child device is probed.
+
+Also the bus driver can define the child_pre_probe() and child_post_remove()
+methods to allow it to do some processing before the child is activated or
+after it is deactivated.
+
+Note that the information that controls this behaviour is in the bus's
+driver, not the child's. In fact it is possible that child has no knowledge
+that it is connected to a bus. The same child device may even be used on two
+different bus types. As an example. the 'flash' device shown above may also
+be connected on a SATA bus or standalone with no bus:
+
+   xhci_usb (UCLASS_USB)
+      flash (UCLASS_FLASH_STORAGE)  - parent data/methods defined by USB bus
+
+   sata (UCLASS_SATA)
+      flash (UCLASS_FLASH_STORAGE)  - parent data/methods defined by SATA bus
+
+   flash (UCLASS_FLASH_STORAGE)  - no parent data/methods (not on a bus)
+
+Above you can see that the driver for xhci_usb/sata controls the child's
+bus methods. In the third example the device is not on a bus, and therefore
+will not have these methods at all. Consider the case where the flash
+device defines child methods. These would be used for *its* children, and
+would be quite separate from the methods defined by the driver for the bus
+that the flash device is connetced to. The act of attaching a device to a
+parent device which is a bus, causes the device to start behaving like a
+bus device, regardless of its own views on the matter.
+
+The uclass for the device can also contain data private to that uclass.
+But note that each device on the bus may be a memeber of a different
+uclass, and this data has nothing to do with the child data for each child
+on the bus.
+
+
 Driver Lifecycle
 ----------------
 
@@ -406,12 +556,23 @@ steps (see device_probe()):
    stored in the device, but it is uclass data. owned by the uclass driver.
    It is possible for the device to access it.
 
-   d. All parent devices are probed. It is not possible to activate a device
+   d. If the device's immediate parent specifies a per_child_auto_alloc_size
+   then this space is allocated. This is intended for use by the parent
+   device to keep track of things related to the child. For example a USB
+   flash stick attached to a USB host controller would likely use this
+   space. The controller can hold information about the USB state of each
+   of its children.
+
+   e. All parent devices are probed. It is not possible to activate a device
    unless its predecessors (all the way up to the root device) are activated.
    This means (for example) that an I2C driver will require that its bus
    be activated.
 
-   e. If the driver provides an ofdata_to_platdata() method, then this is
+   f. The device's sequence number is assigned, either the requested one
+   (assuming no conflicts) or the next available one if there is a conflict
+   or nothing particular is requested.
+
+   g. If the driver provides an ofdata_to_platdata() method, then this is
    called to convert the device tree data into platform data. This should
    do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...)
    to access the node and store the resulting information into dev->platdata.
@@ -427,7 +588,7 @@ steps (see device_probe()):
    data, one day it is possible that U-Boot will cache platformat data for
    devices which are regularly de/activated).
 
-   f. The device's probe() method is called. This should do anything that
+   h. The device's probe() method is called. This should do anything that
    is required by the device to get it going. This could include checking
    that the hardware is actually present, setting up clocks for the
    hardware and setting up hardware registers to initial values. The code
@@ -442,9 +603,9 @@ steps (see device_probe()):
    allocate the priv space here yourself. The same applies also to
    platdata_auto_alloc_size. Remember to free them in the remove() method.
 
-   g. The device is marked 'activated'
+   i. The device is marked 'activated'
 
-   h. The uclass's post_probe() method is called, if one exists. This may
+   j. The uclass's post_probe() method is called, if one exists. This may
    cause the uclass to do some housekeeping to record the device as
    activated and 'known' by the uclass.
 
@@ -475,7 +636,8 @@ remove it. This performs the probe steps in reverse:
    to be sure that no hardware is running, it should be enough to remove
    all devices.
 
-   d. The device memory is freed (platform data, private data, uclass data).
+   d. The device memory is freed (platform data, private data, uclass data,
+   parent data).
 
    Note: Because the platform data for a U_BOOT_DEVICE() is defined with a
    static pointer, it is not de-allocated during the remove() method. For
@@ -490,7 +652,14 @@ remove it. This performs the probe steps in reverse:
       or preferably ofdata_to_platdata()) and the deallocation in remove()
       are the responsibility of the driver author.
 
-   e. The device is marked inactive. Note that it is still bound, so the
+   e. The device sequence number is set to -1, meaning that it no longer
+   has an allocated sequence. If the device is later reactivated and that
+   sequence number is still free, it may well receive the name sequence
+   number again. But from this point, the sequence number previously used
+   by this device will no longer exist (think of SPI bus 2 being removed
+   and bus 2 is no longer available for use).
+
+   f. The device is marked inactive. Note that it is still bound, so the
    device structure itself is not freed at this point. Should the device be
    activated again, then the cycle starts again at step 2 above.
 
@@ -538,26 +707,35 @@ dealing with this might not be worth it.
 - Implemented a GPIO system, trying to keep it simple
 
 
+Pre-Relocation Support
+----------------------
+
+For pre-relocation we simply call the driver model init function. Only
+drivers marked with DM_FLAG_PRE_RELOC or the device tree
+'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps
+to reduce the driver model overhead.
+
+Then post relocation we throw that away and re-init driver model again.
+For drivers which require some sort of continuity between pre- and
+post-relocation devices, we can provide access to the pre-relocation
+device pointers, but this is not currently implemented (the root device
+pointer is saved but not made available through the driver model API).
+
+
 Things to punt for later
 ------------------------
 
 - SPL support - this will have to be present before many drivers can be
 converted, but it seems like we can add it once we are happy with the
 core implementation.
-- Pre-relocation support - similar story
 
-That is not to say that no thinking has gone into these - in fact there
+That is not to say that no thinking has gone into this - in fact there
 is quite a lot there. However, getting these right is non-trivial and
 there is a high cost associated with going down the wrong path.
 
 For SPL, it may be possible to fit in a simplified driver model with only
 bind and probe methods, to reduce size.
 
-For pre-relocation we can simply call the driver model init function. Then
-post relocation we throw that away and re-init driver model again. For drivers
-which require some sort of continuity between pre- and post-relocation
-devices, we can provide access to the pre-relocation device pointers.
-
 Uclasses are statically numbered at compile time. It would be possible to
 change this to dynamic numbering, but then we would require some sort of
 lookup service, perhaps searching by name. This is slightly less efficient
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c8f65739e9..4df804671a 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_SPINUP	20000
 #define WAIT_MS_DATAIO	5000
 #define WAIT_MS_FLUSH	5000
-#define WAIT_MS_LINKUP	40
+#define WAIT_MS_LINKUP	200
 
 static inline u32 ahci_port_base(u32 base, u32 port)
 {
diff --git a/drivers/core/device.c b/drivers/core/device.c
index c73c339d18..166b0732ab 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <malloc.h>
 #include <dm/device.h>
 #include <dm/device-internal.h>
@@ -21,6 +22,8 @@
 #include <linux/err.h>
 #include <linux/list.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /**
  * device_chld_unbind() - Unbind all device's children from the device
  *
@@ -95,6 +98,21 @@ int device_bind(struct udevice *parent, struct driver *drv, const char *name,
 	dev->parent = parent;
 	dev->driver = drv;
 	dev->uclass = uc;
+
+	/*
+	 * For some devices, such as a SPI or I2C bus, the 'reg' property
+	 * is a reasonable indicator of the sequence number. But if there is
+	 * an alias, we use that in preference. In any case, this is just
+	 * a 'requested' sequence, and will be resolved (and ->seq updated)
+	 * when the device is probed.
+	 */
+	dev->req_seq = fdtdec_get_int(gd->fdt_blob, of_offset, "reg", -1);
+	dev->seq = -1;
+	if (uc->uc_drv->name && of_offset != -1) {
+		fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name, of_offset,
+				     &dev->req_seq);
+	}
+
 	if (!dev->platdata && drv->platdata_auto_alloc_size)
 		dev->flags |= DM_FLAG_ALLOC_PDATA;
 
@@ -129,14 +147,16 @@ fail_bind:
 	return ret;
 }
 
-int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
-			struct udevice **devp)
+int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
+			const struct driver_info *info, struct udevice **devp)
 {
 	struct driver *drv;
 
 	drv = lists_driver_lookup_name(info->name);
 	if (!drv)
 		return -ENOENT;
+	if (pre_reloc_only && !(drv->flags & DM_FLAG_PRE_RELOC))
+		return -EPERM;
 
 	return device_bind(parent, drv, info->name, (void *)info->platdata,
 			   -1, devp);
@@ -198,6 +218,13 @@ static void device_free(struct udevice *dev)
 		free(dev->uclass_priv);
 		dev->uclass_priv = NULL;
 	}
+	if (dev->parent) {
+		size = dev->parent->driver->per_child_auto_alloc_size;
+		if (size) {
+			free(dev->parent_priv);
+			dev->parent_priv = NULL;
+		}
+	}
 }
 
 int device_probe(struct udevice *dev)
@@ -205,6 +232,7 @@ int device_probe(struct udevice *dev)
 	struct driver *drv;
 	int size = 0;
 	int ret;
+	int seq;
 
 	if (!dev)
 		return -EINVAL;
@@ -242,11 +270,33 @@ int device_probe(struct udevice *dev)
 
 	/* Ensure all parents are probed */
 	if (dev->parent) {
+		size = dev->parent->driver->per_child_auto_alloc_size;
+		if (size) {
+			dev->parent_priv = calloc(1, size);
+			if (!dev->parent_priv) {
+				ret = -ENOMEM;
+				goto fail;
+			}
+		}
+
 		ret = device_probe(dev->parent);
 		if (ret)
 			goto fail;
 	}
 
+	seq = uclass_resolve_seq(dev);
+	if (seq < 0) {
+		ret = seq;
+		goto fail;
+	}
+	dev->seq = seq;
+
+	if (dev->parent && dev->parent->driver->child_pre_probe) {
+		ret = dev->parent->driver->child_pre_probe(dev);
+		if (ret)
+			goto fail;
+	}
+
 	if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
 		ret = drv->ofdata_to_platdata(dev);
 		if (ret)
@@ -274,6 +324,7 @@ fail_uclass:
 			__func__, dev->name);
 	}
 fail:
+	dev->seq = -1;
 	device_free(dev);
 
 	return ret;
@@ -307,11 +358,20 @@ int device_remove(struct udevice *dev)
 			goto err_remove;
 	}
 
+	if (dev->parent && dev->parent->driver->child_post_remove) {
+		ret = dev->parent->driver->child_post_remove(dev);
+		if (ret) {
+			dm_warn("%s: Device '%s' failed child_post_remove()",
+				__func__, dev->name);
+		}
+	}
+
 	device_free(dev);
 
+	dev->seq = -1;
 	dev->flags &= ~DM_FLAG_ACTIVATED;
 
-	return 0;
+	return ret;
 
 err_remove:
 	/* We can't put the children back */
@@ -346,3 +406,106 @@ void *dev_get_priv(struct udevice *dev)
 
 	return dev->priv;
 }
+
+void *dev_get_parentdata(struct udevice *dev)
+{
+	if (!dev) {
+		dm_warn("%s: null device", __func__);
+		return NULL;
+	}
+
+	return dev->parent_priv;
+}
+
+static int device_get_device_tail(struct udevice *dev, int ret,
+				  struct udevice **devp)
+{
+	if (ret)
+		return ret;
+
+	ret = device_probe(dev);
+	if (ret)
+		return ret;
+
+	*devp = dev;
+
+	return 0;
+}
+
+int device_get_child(struct udevice *parent, int index, struct udevice **devp)
+{
+	struct udevice *dev;
+
+	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+		if (!index--)
+			return device_get_device_tail(dev, 0, devp);
+	}
+
+	return -ENODEV;
+}
+
+int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
+			     bool find_req_seq, struct udevice **devp)
+{
+	struct udevice *dev;
+
+	*devp = NULL;
+	if (seq_or_req_seq == -1)
+		return -ENODEV;
+
+	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+		if ((find_req_seq ? dev->req_seq : dev->seq) ==
+				seq_or_req_seq) {
+			*devp = dev;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+int device_get_child_by_seq(struct udevice *parent, int seq,
+			    struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = device_find_child_by_seq(parent, seq, false, &dev);
+	if (ret == -ENODEV) {
+		/*
+		 * We didn't find it in probed devices. See if there is one
+		 * that will request this seq if probed.
+		 */
+		ret = device_find_child_by_seq(parent, seq, true, &dev);
+	}
+	return device_get_device_tail(dev, ret, devp);
+}
+
+int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
+				   struct udevice **devp)
+{
+	struct udevice *dev;
+
+	*devp = NULL;
+
+	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+		if (dev->of_offset == of_offset) {
+			*devp = dev;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+int device_get_child_by_of_offset(struct udevice *parent, int seq,
+				  struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = device_find_child_by_of_offset(parent, seq, &dev);
+	return device_get_device_tail(dev, ret, devp);
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index afb59d1d8d..0f08bfd6ff 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -11,6 +11,7 @@
 #include <errno.h>
 #include <dm/device.h>
 #include <dm/device-internal.h>
+#include <dm/lists.h>
 #include <dm/platdata.h>
 #include <dm/uclass.h>
 #include <dm/util.h>
@@ -61,7 +62,7 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id)
 	return NULL;
 }
 
-int lists_bind_drivers(struct udevice *parent)
+int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only)
 {
 	struct driver_info *info =
 		ll_entry_start(struct driver_info, driver_info);
@@ -72,8 +73,8 @@ int lists_bind_drivers(struct udevice *parent)
 	int ret;
 
 	for (entry = info; entry != info + n_ents; entry++) {
-		ret = device_bind_by_name(parent, entry, &dev);
-		if (ret) {
+		ret = device_bind_by_name(parent, pre_reloc_only, entry, &dev);
+		if (ret && ret != -EPERM) {
 			dm_warn("No match for driver '%s'\n", entry->name);
 			if (!result || ret != -ENOENT)
 				result = ret;
@@ -123,16 +124,19 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset)
 	const int n_ents = ll_entry_count(struct driver, driver);
 	struct driver *entry;
 	struct udevice *dev;
+	bool found = false;
 	const char *name;
 	int result = 0;
-	int ret;
+	int ret = 0;
 
 	dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
 	for (entry = driver; entry != driver + n_ents; entry++) {
 		ret = driver_check_compatible(blob, offset, entry->of_match);
+		name = fdt_get_name(blob, offset, NULL);
 		if (ret == -ENOENT) {
 			continue;
 		} else if (ret == -ENODEV) {
+			dm_dbg("Device '%s' has no compatible string\n", name);
 			break;
 		} else if (ret) {
 			dm_warn("Device tree error at offset %d\n", offset);
@@ -141,14 +145,21 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset)
 			break;
 		}
 
-		name = fdt_get_name(blob, offset, NULL);
 		dm_dbg("   - found match at '%s'\n", entry->name);
 		ret = device_bind(parent, entry, name, NULL, offset, &dev);
 		if (ret) {
-			dm_warn("No match for driver '%s'\n", entry->name);
+			dm_warn("Error binding driver '%s'\n", entry->name);
 			if (!result || ret != -ENOENT)
 				result = ret;
+		} else {
+			found = true;
 		}
+		break;
+	}
+
+	if (!found && !result && ret != -ENODEV) {
+		dm_dbg("No match for node '%s'\n",
+		       fdt_get_name(blob, offset, NULL));
 	}
 
 	return result;
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 1cbb096494..393dd98b9d 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -15,6 +15,7 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/platdata.h>
+#include <dm/root.h>
 #include <dm/uclass.h>
 #include <dm/util.h>
 #include <linux/list.h>
@@ -45,18 +46,29 @@ int dm_init(void)
 	}
 	INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST);
 
-	ret = device_bind_by_name(NULL, &root_info, &DM_ROOT_NON_CONST);
+	ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
 	if (ret)
 		return ret;
+	ret = device_probe(DM_ROOT_NON_CONST);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int dm_uninit(void)
+{
+	device_remove(dm_root());
+	device_unbind(dm_root());
 
 	return 0;
 }
 
-int dm_scan_platdata(void)
+int dm_scan_platdata(bool pre_reloc_only)
 {
 	int ret;
 
-	ret = lists_bind_drivers(DM_ROOT_NON_CONST);
+	ret = lists_bind_drivers(DM_ROOT_NON_CONST, pre_reloc_only);
 	if (ret == -ENOENT) {
 		dm_warn("Some drivers were not found\n");
 		ret = 0;
@@ -68,27 +80,66 @@ int dm_scan_platdata(void)
 }
 
 #ifdef CONFIG_OF_CONTROL
-int dm_scan_fdt(const void *blob)
+int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
+		     bool pre_reloc_only)
 {
-	int offset = 0;
 	int ret = 0, err;
-	int depth = 0;
 
-	do {
-		offset = fdt_next_node(blob, offset, &depth);
-		if (offset > 0 && depth == 1) {
-			err = lists_bind_fdt(gd->dm_root, blob, offset);
-			if (err && !ret)
-				ret = err;
-		}
-	} while (offset > 0);
+	for (offset = fdt_first_subnode(blob, offset);
+	     offset > 0;
+	     offset = fdt_next_subnode(blob, offset)) {
+		if (pre_reloc_only &&
+		    !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL))
+			continue;
+		err = lists_bind_fdt(parent, blob, offset);
+		if (err && !ret)
+			ret = err;
+	}
 
 	if (ret)
 		dm_warn("Some drivers failed to bind\n");
 
 	return ret;
 }
+
+int dm_scan_fdt(const void *blob, bool pre_reloc_only)
+{
+	return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
+}
+#endif
+
+__weak int dm_scan_other(bool pre_reloc_only)
+{
+	return 0;
+}
+
+int dm_init_and_scan(bool pre_reloc_only)
+{
+	int ret;
+
+	ret = dm_init();
+	if (ret) {
+		debug("dm_init() failed: %d\n", ret);
+		return ret;
+	}
+	ret = dm_scan_platdata(pre_reloc_only);
+	if (ret) {
+		debug("dm_scan_platdata() failed: %d\n", ret);
+		return ret;
+	}
+#ifdef CONFIG_OF_CONTROL
+	ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+	if (ret) {
+		debug("dm_scan_fdt() failed: %d\n", ret);
+		return ret;
+	}
 #endif
+	ret = dm_scan_other(pre_reloc_only);
+	if (ret)
+		return ret;
+
+	return 0;
+}
 
 /* This is the root driver - all drivers are children of this */
 U_BOOT_DRIVER(root_driver) = {
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 34723ec42a..61ca17e564 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -23,6 +23,8 @@ struct uclass *uclass_find(enum uclass_id key)
 {
 	struct uclass *uc;
 
+	if (!gd->dm_root)
+		return NULL;
 	/*
 	 * TODO(sjg@chromium.org): Optimise this, perhaps moving the found
 	 * node to the start of the list, or creating a linear array mapping
@@ -158,13 +160,72 @@ int uclass_find_device(enum uclass_id id, int index, struct udevice **devp)
 	return -ENODEV;
 }
 
-int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
+int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
+			      bool find_req_seq, struct udevice **devp)
 {
+	struct uclass *uc;
 	struct udevice *dev;
 	int ret;
 
 	*devp = NULL;
-	ret = uclass_find_device(id, index, &dev);
+	debug("%s: %d %d\n", __func__, find_req_seq, seq_or_req_seq);
+	if (seq_or_req_seq == -1)
+		return -ENODEV;
+	ret = uclass_get(id, &uc);
+	if (ret)
+		return ret;
+
+	list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+		debug("   - %d %d\n", dev->req_seq, dev->seq);
+		if ((find_req_seq ? dev->req_seq : dev->seq) ==
+				seq_or_req_seq) {
+			*devp = dev;
+			debug("   - found\n");
+			return 0;
+		}
+	}
+	debug("   - not found\n");
+
+	return -ENODEV;
+}
+
+static int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+					   struct udevice **devp)
+{
+	struct uclass *uc;
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	if (node < 0)
+		return -ENODEV;
+	ret = uclass_get(id, &uc);
+	if (ret)
+		return ret;
+
+	list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+		if (dev->of_offset == node) {
+			*devp = dev;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+/**
+ * uclass_get_device_tail() - handle the end of a get_device call
+ *
+ * This handles returning an error or probing a device as needed.
+ *
+ * @dev: Device that needs to be probed
+ * @ret: Error to return. If non-zero then the device is not probed
+ * @devp: Returns the value of 'dev' if there is no error
+ * @return ret, if non-zero, else the result of the device_probe() call
+ */
+static int uclass_get_device_tail(struct udevice *dev, int ret,
+				  struct udevice **devp)
+{
 	if (ret)
 		return ret;
 
@@ -177,6 +238,44 @@ int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
 	return 0;
 }
 
+int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_find_device(id, index, &dev);
+	return uclass_get_device_tail(dev, ret, devp);
+}
+
+int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_find_device_by_seq(id, seq, false, &dev);
+	if (ret == -ENODEV) {
+		/*
+		 * We didn't find it in probed devices. See if there is one
+		 * that will request this seq if probed.
+		 */
+		ret = uclass_find_device_by_seq(id, seq, true, &dev);
+	}
+	return uclass_get_device_tail(dev, ret, devp);
+}
+
+int uclass_get_device_by_of_offset(enum uclass_id id, int node,
+				   struct udevice **devp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*devp = NULL;
+	ret = uclass_find_device_by_of_offset(id, node, &dev);
+	return uclass_get_device_tail(dev, ret, devp);
+}
+
 int uclass_first_device(enum uclass_id id, struct udevice **devp)
 {
 	struct uclass *uc;
@@ -254,6 +353,37 @@ int uclass_unbind_device(struct udevice *dev)
 	return 0;
 }
 
+int uclass_resolve_seq(struct udevice *dev)
+{
+	struct udevice *dup;
+	int seq;
+	int ret;
+
+	assert(dev->seq == -1);
+	ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq,
+					false, &dup);
+	if (!ret) {
+		dm_warn("Device '%s': seq %d is in use by '%s'\n",
+			dev->name, dev->req_seq, dup->name);
+	} else if (ret == -ENODEV) {
+		/* Our requested sequence number is available */
+		if (dev->req_seq != -1)
+			return dev->req_seq;
+	} else {
+		return ret;
+	}
+
+	for (seq = 0; seq < DM_MAX_SEQ; seq++) {
+		ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
+						false, &dup);
+		if (ret == -ENODEV)
+			break;
+		if (ret)
+			return ret;
+	}
+	return seq;
+}
+
 int uclass_post_probe_device(struct udevice *dev)
 {
 	struct uclass_driver *uc_drv = dev->uclass->uc_drv;
@@ -281,6 +411,7 @@ int uclass_pre_remove_device(struct udevice *dev)
 		free(dev->uclass_priv);
 		dev->uclass_priv = NULL;
 	}
+	dev->seq = -1;
 
 	return 0;
 }
diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c
index 636fd8831f..f6510d602c 100644
--- a/drivers/demo/demo-uclass.c
+++ b/drivers/demo/demo-uclass.c
@@ -19,6 +19,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 UCLASS_DRIVER(demo) = {
+	.name		= "demo",
 	.id		= UCLASS_DEMO,
 };
 
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4e001e12bd..aa11f15423 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
+endif
 
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
@@ -34,3 +36,4 @@ obj-$(CONFIG_XILINX_GPIO)	+= xilinx_gpio.o
 obj-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
 obj-$(CONFIG_TCA642X)		+= tca642x.o
 oby-$(CONFIG_SX151X)		+= sx151x.o
+obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
new file mode 100644
index 0000000000..0c50a8f332
--- /dev/null
+++ b/drivers/gpio/sunxi_gpio.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+static int sunxi_gpio_output(u32 pin, u32 val)
+{
+	u32 dat;
+	u32 bank = GPIO_BANK(pin);
+	u32 num = GPIO_NUM(pin);
+	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+	dat = readl(&pio->dat);
+	if (val)
+		dat |= 0x1 << num;
+	else
+		dat &= ~(0x1 << num);
+
+	writel(dat, &pio->dat);
+
+	return 0;
+}
+
+static int sunxi_gpio_input(u32 pin)
+{
+	u32 dat;
+	u32 bank = GPIO_BANK(pin);
+	u32 num = GPIO_NUM(pin);
+	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+	dat = readl(&pio->dat);
+	dat >>= num;
+
+	return dat & 0x1;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+	return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
+
+	return sunxi_gpio_input(gpio);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
+
+	return sunxi_gpio_output(gpio, value);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	return sunxi_gpio_input(gpio);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+	return sunxi_gpio_output(gpio, value);
+}
+
+int sunxi_name_to_gpio(const char *name)
+{
+	int group = 0;
+	int groupsize = 9 * 32;
+	long pin;
+	char *eptr;
+	if (*name == 'P' || *name == 'p')
+		name++;
+	if (*name >= 'A') {
+		group = *name - (*name > 'a' ? 'a' : 'A');
+		groupsize = 32;
+		name++;
+	}
+
+	pin = simple_strtol(name, &eptr, 10);
+	if (!*name || *eptr)
+		return -1;
+	if (pin < 0 || pin > groupsize || group >= 9)
+		return -1;
+	return group * 32 + pin;
+}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 96bd45d853..416ea4f2c8 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -7,7 +7,6 @@
 
 obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 obj-$(CONFIG_DW_I2C) += designware_i2c.o
-obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
 obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
@@ -20,6 +19,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index aa159f8d41..811033b0b8 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -46,10 +46,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct fsl_i2c *i2c_dev[2] = {
+static const struct fsl_i2c *i2c_dev[4] = {
 	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
+	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
 #endif
 };
 
@@ -539,3 +545,15 @@ U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
 			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
 			 1)
 #endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+			 fsl_i2c_write, fsl_i2c_set_bus_speed,
+			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
+			 2)
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+			 fsl_i2c_write, fsl_i2c_set_bus_speed,
+			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
+			 3)
+#endif
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 5ba0e03862..ab3ffa0fc1 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -22,6 +22,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_SUNXI)
+#include <asm/arch/i2c.h>
 #else
 #error Driver mvtwsi not supported by SoC or board
 #endif
@@ -30,6 +32,20 @@
  * TWSI register structure
  */
 
+#ifdef CONFIG_SUNXI
+
+struct  mvtwsi_registers {
+	u32 slave_address;
+	u32 xtnd_slave_addr;
+	u32 data;
+	u32 control;
+	u32 status;
+	u32 baudrate;
+	u32 soft_reset;
+};
+
+#else
+
 struct  mvtwsi_registers {
 	u32 slave_address;
 	u32 data;
@@ -43,6 +59,8 @@ struct  mvtwsi_registers {
 	u32 soft_reset;
 };
 
+#endif
+
 /*
  * Control register fields
  */
@@ -220,11 +238,10 @@ static int twsi_stop(int status)
 
 /*
  * Reset controller.
- * Called at end of i2c_init unsuccessful i2c transactions.
  * Controller reset also resets the baud rate and slave address, so
- * re-establish them.
+ * they must be re-established afterwards.
  */
-static void twsi_reset(u8 baud_rate, u8 slave_address)
+static void twsi_reset(struct i2c_adapter *adap)
 {
 	/* ensure controller will be enabled by any twsi*() function */
 	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
@@ -232,23 +249,17 @@ static void twsi_reset(u8 baud_rate, u8 slave_address)
 	writel(0, &twsi->soft_reset);
 	/* wait 2 ms -- this is what the Marvell LSP does */
 	udelay(20000);
-	/* set baud rate */
-	writel(baud_rate, &twsi->baudrate);
-	/* set slave address even though we don't use it */
-	writel(slave_address, &twsi->slave_address);
-	writel(0, &twsi->xtnd_slave_addr);
-	/* assert STOP but don't care for the result */
-	(void) twsi_stop(0);
 }
 
 /*
  * I2C init called by cmd_i2c when doing 'i2c reset'.
  * Sets baud to the highest possible value not exceeding requested one.
  */
-void i2c_init(int requested_speed, int slaveadd)
+static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+					   unsigned int requested_speed)
 {
-	int	tmp_speed, highest_speed, n, m;
-	int	baud = 0x44; /* baudrate at controller reset */
+	unsigned int tmp_speed, highest_speed, n, m;
+	unsigned int baud = 0x44; /* baudrate at controller reset */
 
 	/* use actual speed to collect progressively higher values */
 	highest_speed = 0;
@@ -263,8 +274,21 @@ void i2c_init(int requested_speed, int slaveadd)
 			}
 		}
 	}
+	writel(baud, &twsi->baudrate);
+	return 0;
+}
+
+static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
 	/* reset controller */
-	twsi_reset(baud, slaveadd);
+	twsi_reset(adap);
+	/* set speed */
+	twsi_i2c_set_bus_speed(adap, speed);
+	/* set slave address even though we don't use it */
+	writel(slaveadd, &twsi->slave_address);
+	writel(0, &twsi->xtnd_slave_addr);
+	/* assert STOP but don't care for the result */
+	(void) twsi_stop(0);
 }
 
 /*
@@ -294,7 +318,7 @@ static int i2c_begin(int expected_start_status, u8 addr)
  * I2C probe called by cmd_i2c when doing 'i2c probe'.
  * Begin read, nak data byte, end.
  */
-int i2c_probe(uchar chip)
+static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	u8 dummy_byte;
 	int status;
@@ -320,12 +344,13 @@ int i2c_probe(uchar chip)
  * cmd_eeprom, so we have to choose here, and for the moment that'll be
  * a repeated start without a preceding stop.
  */
-int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			int alen, uchar *data, int length)
 {
 	int status;
 
 	/* begin i2c write to send the address bytes */
-	status = i2c_begin(MVTWSI_STATUS_START, (dev << 1));
+	status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(addr >> (8*alen),
@@ -333,7 +358,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 	/* begin i2c read to receive eeprom data bytes */
 	if (status == 0)
 		status = i2c_begin(
-			MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1);
+			MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
 	/* prepare ACK if at least one byte must be received */
 	if (length > 0)
 		twsi_control_flags |= MVTWSI_CONTROL_ACK;
@@ -355,12 +380,13 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  * Begin write, send address byte(s), send data bytes, end.
  */
-int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			int alen, uchar *data, int length)
 {
 	int status;
 
 	/* begin i2c write to send the eeprom adress bytes then data bytes */
-	status = i2c_begin(MVTWSI_STATUS_START, (dev << 1));
+	status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(addr >> (8*alen),
@@ -374,21 +400,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 	return status;
 }
 
-/*
- * Bus set routine: we only support bus 0.
- */
-int i2c_set_bus_num(unsigned int bus)
-{
-	if (bus > 0) {
-		return -1;
-	}
-	return 0;
-}
-
-/*
- * Bus get routine: hard-return bus 0.
- */
-unsigned int i2c_get_bus_num(void)
-{
-	return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
+			 twsi_i2c_read, twsi_i2c_write,
+			 twsi_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index a39b5917ec..0f1e35c460 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -153,11 +153,60 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 
 	return 0;
 }
+
+static void omap24_i2c_deblock(struct i2c_adapter *adap)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+	int i;
+	u16 systest;
+	u16 orgsystest;
+
+	/* set test mode ST_EN = 1 */
+	orgsystest = readw(&i2c_base->systest);
+	systest = orgsystest;
+	/* enable testmode */
+	systest |= I2C_SYSTEST_ST_EN;
+	writew(systest, &i2c_base->systest);
+	systest &= ~I2C_SYSTEST_TMODE_MASK;
+	systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
+	writew(systest, &i2c_base->systest);
+
+	/* set SCL, SDA  = 1 */
+	systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
+	writew(systest, &i2c_base->systest);
+	udelay(10);
+
+	/* toggle scl 9 clocks */
+	for (i = 0; i < 9; i++) {
+		/* SCL = 0 */
+		systest &= ~I2C_SYSTEST_SCL_O;
+		writew(systest, &i2c_base->systest);
+		udelay(10);
+		/* SCL = 1 */
+		systest |= I2C_SYSTEST_SCL_O;
+		writew(systest, &i2c_base->systest);
+		udelay(10);
+	}
+
+	/* send stop */
+	systest &= ~I2C_SYSTEST_SDA_O;
+	writew(systest, &i2c_base->systest);
+	udelay(10);
+	systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
+	writew(systest, &i2c_base->systest);
+	udelay(10);
+
+	/* restore original mode */
+	writew(orgsystest, &i2c_base->systest);
+}
+
 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	struct i2c *i2c_base = omap24_get_base(adap);
 	int timeout = I2C_TIMEOUT;
+	int deblock = 1;
 
+retry:
 	if (readw(&i2c_base->con) & I2C_CON_EN) {
 		writew(0, &i2c_base->con);
 		udelay(50000);
@@ -194,6 +243,14 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 	udelay(1000);
 	flush_fifo(adap);
 	writew(0xFFFF, &i2c_base->stat);
+
+	/* Handle possible failed I2C state */
+	if (wait_for_bb(adap))
+		if (deblock == 1) {
+			omap24_i2c_deblock(adap);
+			deblock = 0;
+			goto retry;
+		}
 }
 
 static void flush_fifo(struct i2c_adapter *adap)
diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c
index a2501e0206..47502b1763 100644
--- a/drivers/input/cros_ec_keyb.c
+++ b/drivers/input/cros_ec_keyb.c
@@ -93,7 +93,7 @@ static int check_for_keys(struct keyb *config,
  *
  * @return 0 if no keys available, 1 if keys are available
  */
-static int kbd_tstc(void)
+static int kbd_tstc(struct stdio_dev *dev)
 {
 	/* Just get input to do this for us */
 	return config.inited ? input_tstc(&config.input) : 0;
@@ -104,7 +104,7 @@ static int kbd_tstc(void)
  *
  * @return ASCII key code, or 0 if no key, or -1 if error
  */
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
 {
 	/* Just get input to do this for us */
 	return config.inited ? input_getc(&config.input) : 0;
@@ -214,7 +214,7 @@ static int cros_ec_keyb_decode_fdt(const void *blob, int node,
  *
  * @return 0 if ok, -1 on error
  */
-static int cros_ec_init_keyboard(void)
+static int cros_ec_init_keyboard(struct stdio_dev *dev)
 {
 	const void *blob = gd->fdt_blob;
 	int node;
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 35fa0bb504..ca1604c540 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -398,7 +398,7 @@ int i8042_kbd_init(void)
  * i8042_tstc - test if keyboard input is available
  *		option: cursor blinking if called in a loop
  */
-int i8042_tstc(void)
+int i8042_tstc(struct stdio_dev *dev)
 {
 	unsigned char scan_code = 0;
 
@@ -432,7 +432,7 @@ int i8042_tstc(void)
  * i8042_getc - wait till keyboard input is available
  *		option: turn on/off cursor while waiting
  */
-int i8042_getc(void)
+int i8042_getc(struct stdio_dev *dev)
 {
 	int ret_chr;
 	unsigned char scan_code;
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index 614592ef3c..be0f3330db 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -70,7 +70,7 @@ static void kbd_put_queue(char data)
 }
 
 /* test if a character is in the queue */
-static int kbd_testc(void)
+static int kbd_testc(struct stdio_dev *dev)
 {
 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
 	/* no ISR is used, so received chars must be polled */
@@ -83,7 +83,7 @@ static int kbd_testc(void)
 }
 
 /* gets the character from the queue */
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
 {
 	char c;
 	while(in_pointer==out_pointer) {
@@ -275,8 +275,6 @@ int kbd_init (void)
 	memset (&kbddev, 0, sizeof(kbddev));
 	strcpy(kbddev.name, DEVNAME);
 	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-	kbddev.putc = NULL ;
-	kbddev.puts = NULL ;
 	kbddev.getc = kbd_getc ;
 	kbddev.tstc = kbd_testc ;
 
diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c
index f137f930a9..7e36db0a71 100644
--- a/drivers/input/tegra-kbc.c
+++ b/drivers/input/tegra-kbc.c
@@ -194,7 +194,7 @@ int tegra_kbc_check(struct input_config *input)
  *
  * @return 0 if no keys available, 1 if keys are available
  */
-static int kbd_tstc(void)
+static int kbd_tstc(struct stdio_dev *dev)
 {
 	/* Just get input to do this for us */
 	return input_tstc(&config.input);
@@ -207,7 +207,7 @@ static int kbd_tstc(void)
  *
  * @return ASCII key code, or 0 if no key, or -1 if error
  */
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
 {
 	/* Just get input to do this for us */
 	return input_getc(&config.input);
@@ -289,7 +289,7 @@ static void tegra_kbc_open(void)
  *
  * @return 0 if ok, -ve on error
  */
-static int init_tegra_keyboard(void)
+static int init_tegra_keyboard(struct stdio_dev *dev)
 {
 	/* check if already created */
 	if (config.created)
diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c
index 80a84fdf8f..5f85ccf21e 100644
--- a/drivers/misc/cbmem_console.c
+++ b/drivers/misc/cbmem_console.c
@@ -31,7 +31,7 @@ struct cbmem_console {
 
 static struct cbmem_console *cbmem_console_p;
 
-void cbmemc_putc(char data)
+void cbmemc_putc(struct stdio_dev *dev, char data)
 {
 	int cursor;
 
@@ -40,12 +40,12 @@ void cbmemc_putc(char data)
 		cbmem_console_p->buffer_body[cursor] = data;
 }
 
-void cbmemc_puts(const char *str)
+void cbmemc_puts(struct stdio_dev *dev, const char *str)
 {
 	char c;
 
 	while ((c = *str++) != 0)
-		cbmemc_putc(c);
+		cbmemc_putc(dev, c);
 }
 
 int cbmemc_init(void)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b5477b1271..a26f3cec20 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,7 +21,7 @@
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 
-int __weak board_mmc_getwp(struct mmc *mmc)
+__weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
 }
@@ -42,13 +42,11 @@ int mmc_getwp(struct mmc *mmc)
 	return wp;
 }
 
-int __board_mmc_getcd(struct mmc *mmc) {
+__weak int board_mmc_getcd(struct mmc *mmc)
+{
 	return -1;
 }
 
-int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
-	alias("__board_mmc_getcd")));
-
 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
 	int ret;
@@ -377,7 +375,7 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
 	return 0;
 }
 
-int mmc_send_op_cond(struct mmc *mmc)
+static int mmc_send_op_cond(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int err, i;
@@ -399,7 +397,7 @@ int mmc_send_op_cond(struct mmc *mmc)
 	return IN_PROGRESS;
 }
 
-int mmc_complete_op_cond(struct mmc *mmc)
+static int mmc_complete_op_cond(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int timeout = 1000;
@@ -1371,17 +1369,17 @@ int mmc_set_dsr(struct mmc *mmc, u16 val)
 	return 0;
 }
 
-/*
- * CPU and board-specific MMC initializations.  Aliased function
- * signals caller to move on
- */
-static int __def_mmc_init(bd_t *bis)
+/* CPU-specific MMC initializations */
+__weak int cpu_mmc_init(bd_t *bis)
 {
 	return -1;
 }
 
-int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
-int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
+/* board-specific MMC initializations. */
+__weak int board_mmc_init(bd_t *bis)
+{
+	return -1;
+}
 
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 17cbb0983d..5b0c302069 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -120,7 +120,7 @@ static void omap5_pbias_config(struct mmc *mmc)
 }
 #endif
 
-unsigned char mmc_board_init(struct mmc *mmc)
+static unsigned char mmc_board_init(struct mmc *mmc)
 {
 #if defined(CONFIG_OMAP34XX)
 	t2_t *t2_base = (t2_t *)T2_BASE;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index eb7b1158d6..d4e574fe19 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -16,28 +16,6 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/mmc.h>
 
-struct sunxi_mmc_des {
-	u32 reserved1_1:1;
-	u32 dic:1;		/* disable interrupt on completion */
-	u32 last_des:1;		/* 1-this data buffer is the last buffer */
-	u32 first_des:1;		/* 1-data buffer is the first buffer,
-				   0-data buffer contained in the next
-				   descriptor is 1st buffer */
-	u32 des_chain:1;	/* 1-the 2nd address in the descriptor is the
-				   next descriptor address */
-	u32 end_of_ring:1;	/* 1-last descriptor flag when using dual
-				   data buffer in descriptor */
-	u32 reserved1_2:24;
-	u32 card_err_sum:1;	/* transfer error flag */
-	u32 own:1;		/* des owner:1-idma owns it, 0-host owns it */
-#define SDXC_DES_NUM_SHIFT 16
-#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
-	u32 data_buf1_sz:16;
-	u32 data_buf2_sz:16;
-	u32 buf_addr_ptr1;
-	u32 buf_addr_ptr2;
-};
-
 struct sunxi_mmc_host {
 	unsigned mmc_no;
 	uint32_t *mclkreg;
@@ -189,6 +167,7 @@ static int mmc_core_init(struct mmc *mmc)
 
 	/* Reset controller */
 	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+	udelay(1000);
 
 	return 0;
 }
@@ -204,6 +183,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 	unsigned timeout_msecs = 2000;
 	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 
+	/* Always read / write data through the CPU */
+	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
+
 	for (i = 0; i < (byte_cnt >> 2); i++) {
 		while (readl(&mmchost->reg->status) & status_bit) {
 			if (!timeout_msecs--)
@@ -220,85 +202,6 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 	return 0;
 }
 
-static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
-{
-	struct sunxi_mmc_host *mmchost = mmc->priv;
-	unsigned byte_cnt = data->blocksize * data->blocks;
-	unsigned char *buff;
-	unsigned des_idx = 0;
-	unsigned buff_frag_num =
-		(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
-	unsigned remain;
-	unsigned i, rval;
-	ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
-
-	buff = data->flags & MMC_DATA_READ ?
-	    (unsigned char *)data->dest : (unsigned char *)data->src;
-	remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-
-	flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
-	for (i = 0; i < buff_frag_num; i++, des_idx++) {
-		memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
-		pdes[des_idx].des_chain = 1;
-		pdes[des_idx].own = 1;
-		pdes[des_idx].dic = 1;
-		if (buff_frag_num > 1 && i != buff_frag_num - 1)
-			pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
-		else
-			pdes[des_idx].data_buf1_sz = remain;
-
-		pdes[des_idx].buf_addr_ptr1 =
-		    (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
-		if (i == 0)
-			pdes[des_idx].first_des = 1;
-
-		if (i == buff_frag_num - 1) {
-			pdes[des_idx].dic = 0;
-			pdes[des_idx].last_des = 1;
-			pdes[des_idx].end_of_ring = 1;
-			pdes[des_idx].buf_addr_ptr2 = 0;
-		} else {
-			pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
-		}
-	}
-	flush_cache((unsigned long)pdes,
-		    sizeof(struct sunxi_mmc_des) * (des_idx + 1));
-
-	rval = readl(&mmchost->reg->gctrl);
-	/* Enable DMA */
-	writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE,
-	       &mmchost->reg->gctrl);
-	/* Reset iDMA */
-	writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac);
-	/* Enable iDMA */
-	writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE,
-	       &mmchost->reg->dmac);
-	rval = readl(&mmchost->reg->idie) &
-		~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ);
-	if (data->flags & MMC_DATA_WRITE)
-		rval |= SUNXI_MMC_IDIE_TXIRQ;
-	else
-		rval |= SUNXI_MMC_IDIE_RXIRQ;
-	writel(rval, &mmchost->reg->idie);
-	writel((u32) pdes, &mmchost->reg->dlba);
-	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
-	       &mmchost->reg->ftrglevel);
-
-	return 0;
-}
-
-static void mmc_enable_dma_accesses(struct mmc *mmc, int dma)
-{
-	struct sunxi_mmc_host *mmchost = mmc->priv;
-
-	unsigned int gctrl = readl(&mmchost->reg->gctrl);
-	if (dma)
-		gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
-	else
-		gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
-	writel(gctrl, &mmchost->reg->gctrl);
-}
-
 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
 			 unsigned int done_bit, const char *what)
 {
@@ -327,7 +230,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	unsigned int timeout_msecs;
 	int error = 0;
 	unsigned int status = 0;
-	unsigned int usedma = 0;
 	unsigned int bytecnt = 0;
 
 	if (mmchost->fatal_err)
@@ -378,20 +280,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
 		bytecnt = data->blocksize * data->blocks;
 		debug("trans data %d bytes\n", bytecnt);
-#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
-		if (bytecnt > 64) {
-#else
-		if (0) {
-#endif
-			usedma = 1;
-			mmc_enable_dma_accesses(mmc, 1);
-			ret = mmc_trans_data_by_dma(mmc, data);
-			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-		} else {
-			mmc_enable_dma_accesses(mmc, 0);
-			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
-			ret = mmc_trans_data_by_cpu(mmc, data);
-		}
+		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+		ret = mmc_trans_data_by_cpu(mmc, data);
 		if (ret) {
 			error = readl(&mmchost->reg->rint) & \
 				SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
@@ -405,7 +295,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		goto out;
 
 	if (data) {
-		timeout_msecs = usedma ? 120 * bytecnt : 120;
+		timeout_msecs = 120;
 		debug("cacl timeout %x msec\n", timeout_msecs);
 		error = mmc_rint_wait(mmc, timeout_msecs,
 				      data->blocks > 1 ?
@@ -442,23 +332,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		debug("mmc resp 0x%08x\n", cmd->response[0]);
 	}
 out:
-	if (data && usedma) {
-		/* IDMASTAREG
-		 * IDST[0] : idma tx int
-		 * IDST[1] : idma rx int
-		 * IDST[2] : idma fatal bus error
-		 * IDST[4] : idma descriptor invalid
-		 * IDST[5] : idma error summary
-		 * IDST[8] : idma normal interrupt sumary
-		 * IDST[9] : idma abnormal interrupt sumary
-		 */
-		status = readl(&mmchost->reg->idst);
-		writel(status, &mmchost->reg->idst);
-		writel(0, &mmchost->reg->idie);
-		writel(0, &mmchost->reg->dmac);
-		writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE,
-		       &mmchost->reg->gctrl);
-	}
 	if (error < 0) {
 		writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 		mmc_update_clk(mmc);
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index a389cd101c..c4b5bc1de5 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2360,7 +2360,7 @@ unsigned long flash_init (void)
 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */
 		}
 #ifdef CONFIG_SYS_FLASH_PROTECTION
-		else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
+		else if (strcmp(s, "yes") == 0) {
 			/*
 			 * Only the U-Boot image and it's environment
 			 * is protected, all other sectors are
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 5d425092f4..a079b1e5cf 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -305,6 +305,189 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
 #endif
 };
 
+#if defined CONFIG_KEYSTONE_RBL_NAND
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
+static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
+	.eccbytes = 40,
+	.eccpos = {
+		6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+		22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+		38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+	},
+	.oobfree = {
+		{.offset = 2, .length = 4, },
+		{.offset = 16, .length = 6, },
+		{.offset = 32, .length = 6, },
+		{.offset = 48, .length = 6, },
+	},
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+	.eccbytes = 80,
+	.eccpos = {
+		6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+		22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+		38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+		70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+		86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+		102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
+		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+	},
+	.oobfree = {
+		{.offset = 2, .length = 4, },
+		{.offset = 16, .length = 6, },
+		{.offset = 32, .length = 6, },
+		{.offset = 48, .length = 6, },
+		{.offset = 64, .length = 6, },
+		{.offset = 80, .length = 6, },
+		{.offset = 96, .length = 6, },
+		{.offset = 112, .length = 6, },
+	},
+#endif
+};
+
+#ifdef CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
+#endif
+
+/**
+ * nand_davinci_write_page - write one page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
+ */
+static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				   const uint8_t *buf, int oob_required,
+				   int page, int cached, int raw)
+{
+	int status;
+	int ret = 0;
+	struct nand_ecclayout *saved_ecc_layout;
+
+	/* save current ECC layout and assign Keystone RBL ECC layout */
+	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+		saved_ecc_layout = chip->ecc.layout;
+		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+		mtd->oobavail = chip->ecc.layout->oobavail;
+	}
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+	if (unlikely(raw))
+		status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
+	else
+		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+
+	if (status < 0) {
+		ret = status;
+		goto err;
+	}
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	/*
+	 * See if operation failed and additional status checks are
+	 * available.
+	 */
+	if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+		status = chip->errstat(mtd, chip, FL_WRITING, status, page);
+
+	if (status & NAND_STATUS_FAIL) {
+		ret = -EIO;
+		goto err;
+	}
+
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+	/* Send command to read back the data */
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+	if (chip->verify_buf(mtd, buf, mtd->writesize)) {
+		ret = -EIO;
+		goto err;
+	}
+
+	/* Make sure the next page prog is preceded by a status read */
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+#endif
+err:
+	/* restore ECC layout */
+	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+		chip->ecc.layout = saved_ecc_layout;
+		mtd->oobavail = saved_ecc_layout->oobavail;
+	}
+
+	return ret;
+}
+
+/**
+ * nand_davinci_read_page_hwecc - hardware ECC based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
+ *
+ * Not for syndrome calculating ECC controllers which need a special oob layout.
+ */
+static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int oob_required, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint32_t *eccpos;
+	uint8_t *p = buf;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
+
+	/* save current ECC layout and assign Keystone RBL ECC layout */
+	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+		mtd->oobavail = chip->ecc.layout->oobavail;
+	}
+
+	eccpos = chip->ecc.layout->eccpos;
+
+	/* Read the OOB area first */
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+
+	/* restore ECC layout */
+	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+		chip->ecc.layout = saved_ecc_layout;
+		mtd->oobavail = saved_ecc_layout->oobavail;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_KEYSTONE_RBL_NAND */
+
 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	u32 val;
@@ -604,6 +787,19 @@ static void nand_flash_init(void)
 
 void davinci_nand_init(struct nand_chip *nand)
 {
+#if defined CONFIG_KEYSTONE_RBL_NAND
+	int i;
+	struct nand_ecclayout *layout;
+
+	layout = &nand_keystone_rbl_4bit_layout_oobfirst;
+	layout->oobavail = 0;
+	for (i = 0; layout->oobfree[i].length &&
+	     i < ARRAY_SIZE(layout->oobfree); i++)
+		layout->oobavail += layout->oobfree[i].length;
+
+	nand->write_page = nand_davinci_write_page;
+	nand->ecc.read_page = nand_davinci_read_page_hwecc;
+#endif
 	nand->chip_delay  = 0;
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
 	nand->bbt_options	  |= NAND_BBT_USE_FLASH;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6226cb259f..7cc6b6fc08 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DNET) += dnet.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
 obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 obj-$(CONFIG_ETHOC) += ethoc.o
@@ -51,7 +52,6 @@ obj-$(CONFIG_RTL8169) += rtl8169.o
 obj-$(CONFIG_SH_ETHER) += sh_eth.o
 obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index bd5fba21ce..8ec5161ec6 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -211,6 +211,8 @@ struct cpdma_chan {
 #define chan_read(chan, fld)		__raw_readl((chan)->fld)
 #define chan_read_ptr(chan, fld)	((void *)__raw_readl((chan)->fld))
 
+#define for_active_slave(slave, priv) \
+	slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
 #define for_each_slave(slave, priv) \
 	for (slave = (priv)->slaves; slave != (priv)->slaves + \
 				(priv)->data.slaves; slave++)
@@ -609,7 +611,7 @@ static int cpsw_update_link(struct cpsw_priv *priv)
 	int link = 0;
 	struct cpsw_slave *slave;
 
-	for_each_slave(slave, priv)
+	for_active_slave(slave, priv)
 		cpsw_slave_update_link(slave, priv, &link);
 	priv->mdio_link = readl(&mdio_regs->link);
 	return link;
@@ -785,7 +787,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
 			   ALE_SECURE);
 	cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
 
-	for_each_slave(slave, priv)
+	for_active_slave(slave, priv)
 		cpsw_slave_init(slave, priv);
 
 	cpsw_update_link(priv);
@@ -1013,7 +1015,7 @@ int cpsw_register(struct cpsw_platform_data *data)
 
 	cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
-	for_each_slave(slave, priv)
+	for_active_slave(slave, priv)
 		cpsw_phy_init(dev, slave);
 
 	return 1;
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 65c747e14b..623f7492c7 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -215,7 +215,7 @@ static void nc_send_packet(const char *buf, int len)
 	}
 }
 
-static int nc_start(void)
+static int nc_start(struct stdio_dev *dev)
 {
 	int retval;
 
@@ -235,7 +235,7 @@ static int nc_start(void)
 	return 0;
 }
 
-static void nc_putc(char c)
+static void nc_putc(struct stdio_dev *dev, char c)
 {
 	if (output_recursion)
 		return;
@@ -246,7 +246,7 @@ static void nc_putc(char c)
 	output_recursion = 0;
 }
 
-static void nc_puts(const char *s)
+static void nc_puts(struct stdio_dev *dev, const char *s)
 {
 	int len;
 
@@ -265,7 +265,7 @@ static void nc_puts(const char *s)
 	output_recursion = 0;
 }
 
-static int nc_getc(void)
+static int nc_getc(struct stdio_dev *dev)
 {
 	uchar c;
 
@@ -286,7 +286,7 @@ static int nc_getc(void)
 	return c;
 }
 
-static int nc_tstc(void)
+static int nc_tstc(struct stdio_dev *dev)
 {
 	struct eth_device *eth;
 
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 81e8ddbbc7..451c33e1a1 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -413,7 +413,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7794)
 	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
 #endif
 	/* Configure phy */
@@ -439,7 +440,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
-		defined(CONFIG_R8A7791)
+		defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
 		val = ECMR_RTM;
 #endif
 	} else if (phy->speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index d0d9aaa703..e325a39aac 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -358,7 +358,8 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xE9A00000
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7794)
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR	0xEE700200
 #elif defined(CONFIG_R7S72100)
@@ -569,7 +570,8 @@ enum FELIC_MODE_BIT {
 	ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
 	ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7794)
 	ECMR_RTM = 0x00000004,
 #endif
 
diff --git a/drivers/net/sunxi_wemac.c b/drivers/net/sunxi_emac.c
index 699a381582..5a06d68af7 100644
--- a/drivers/net/sunxi_wemac.c
+++ b/drivers/net/sunxi_emac.c
@@ -1,5 +1,5 @@
 /*
- * sunxi_wemac.c -- Allwinner A10 ethernet driver
+ * sunxi_emac.c -- Allwinner A10 ethernet driver
  *
  * (C) Copyright 2012, Stefan Roese <sr@denx.de>
  *
@@ -7,16 +7,16 @@
  */
 
 #include <common.h>
+#include <linux/err.h>
 #include <malloc.h>
-#include <net.h>
 #include <miiphy.h>
-#include <linux/err.h>
+#include <net.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 
 /* EMAC register  */
-struct wemac_regs {
+struct emac_regs {
 	u32 ctl;	/* 0x00 */
 	u32 tx_mode;	/* 0x04 */
 	u32 tx_flow;	/* 0x08 */
@@ -27,7 +27,7 @@ struct wemac_regs {
 	u32 tx_pl1;	/* 0x1c */
 	u32 tx_sta;	/* 0x20 */
 	u32 tx_io_data;	/* 0x24 */
-	u32 tx_io_data1; /* 0x28 */
+	u32 tx_io_data1;/* 0x28 */
 	u32 tx_tsvl0;	/* 0x2c */
 	u32 tx_tsvh0;	/* 0x30 */
 	u32 tx_tsvl1;	/* 0x34 */
@@ -141,33 +141,33 @@ struct sunxi_sramc_regs {
 
 #define EMAC_MAC_IPGT		0x15
 
-#define EMAC_MAC_NBTB_IPG1	0xC
+#define EMAC_MAC_NBTB_IPG1	0xc
 #define EMAC_MAC_NBTB_IPG2	0x12
 
 #define EMAC_MAC_CW		0x37
-#define EMAC_MAC_RM		0xF
+#define EMAC_MAC_RM		0xf
 
 #define EMAC_MAC_MFL		0x0600
 
 /* Receive status */
-#define EMAC_CRCERR		(1 << 4)
-#define EMAC_LENERR		(3 << 5)
+#define EMAC_CRCERR		(0x1 << 4)
+#define EMAC_LENERR		(0x3 << 5)
 
 #define DMA_CPU_TRRESHOLD	2000
 
-struct wemac_eth_dev {
+struct emac_eth_dev {
 	u32 speed;
 	u32 duplex;
 	u32 phy_configured;
 	int link_printed;
 };
 
-struct wemac_rxhdr {
+struct emac_rxhdr {
 	s16 rx_len;
 	u16 rx_status;
 };
 
-static void wemac_inblk_32bit(void *reg, void *data, int count)
+static void emac_inblk_32bit(void *reg, void *data, int count)
 {
 	int cnt = (count + 3) >> 2;
 
@@ -181,7 +181,7 @@ static void wemac_inblk_32bit(void *reg, void *data, int count)
 	}
 }
 
-static void wemac_outblk_32bit(void *reg, void *data, int count)
+static void emac_outblk_32bit(void *reg, void *data, int count)
 {
 	int cnt = (count + 3) >> 2;
 
@@ -194,14 +194,12 @@ static void wemac_outblk_32bit(void *reg, void *data, int count)
 	}
 }
 
-/*
- * Read a word from phyxcer
- */
-static int wemac_phy_read(const char *devname, unsigned char addr,
+/* Read a word from phyxcer */
+static int emac_phy_read(const char *devname, unsigned char addr,
 			  unsigned char reg, unsigned short *value)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* issue the phy address and reg */
 	writel(addr << 8 | reg, &regs->mac_madr);
@@ -221,14 +219,12 @@ static int wemac_phy_read(const char *devname, unsigned char addr,
 	return 0;
 }
 
-/*
- * Write a word to phyxcer
- */
-static int wemac_phy_write(const char *devname, unsigned char addr,
+/* Write a word to phyxcer */
+static int emac_phy_write(const char *devname, unsigned char addr,
 			   unsigned char reg, unsigned short value)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* issue the phy address and reg */
 	writel(addr << 8 | reg, &regs->mac_madr);
@@ -250,7 +246,7 @@ static int wemac_phy_write(const char *devname, unsigned char addr,
 
 static void emac_setup(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 	u32 reg_val;
 	u16 phy_val;
 	u32 duplex_flag;
@@ -266,7 +262,7 @@ static void emac_setup(struct eth_device *dev)
 	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
 
 	/* Set MAC CTL1 */
-	wemac_phy_read(dev->name, 1, 0, &phy_val);
+	emac_phy_read(dev->name, 1, 0, &phy_val);
 	debug("PHY SETUP, reg 0 value: %x\n", phy_val);
 	duplex_flag = !!(phy_val & (1 << 8));
 
@@ -288,9 +284,9 @@ static void emac_setup(struct eth_device *dev)
 	writel(EMAC_MAC_MFL, &regs->mac_maxf);
 }
 
-static void wemac_reset(struct eth_device *dev)
+static void emac_reset(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	debug("resetting device\n");
 
@@ -302,10 +298,10 @@ static void wemac_reset(struct eth_device *dev)
 	udelay(200);
 }
 
-static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
+static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-	struct wemac_eth_dev *priv = dev->priv;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+	struct emac_eth_dev *priv = dev->priv;
 	u16 phy_reg;
 
 	/* Init EMAC */
@@ -317,10 +313,7 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 	/* Init MAC */
 
 	/* Soft reset MAC */
-	clrbits_le32(&regs->mac_ctl0, 1 << 15);
-
-	/* Set MII clock */
-	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
+	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
 
 	/* Clear RX counter */
 	writel(0x0, &regs->rx_fbc);
@@ -336,14 +329,14 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 
 	mdelay(1);
 
-	wemac_reset(dev);
+	emac_reset(dev);
 
 	/* PHY POWER UP */
-	wemac_phy_read(dev->name, 1, 0, &phy_reg);
-	wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
+	emac_phy_read(dev->name, 1, 0, &phy_reg);
+	emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
 	mdelay(1);
 
-	wemac_phy_read(dev->name, 1, 0, &phy_reg);
+	emac_phy_read(dev->name, 1, 0, &phy_reg);
 
 	priv->speed = miiphy_speed(dev->name, 0);
 	priv->duplex = miiphy_duplex(dev->name, 0);
@@ -357,11 +350,11 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 
 	/* Set EMAC SPEED depend on PHY */
 	clrsetbits_le32(&regs->mac_supp, 1 << 8,
-			((phy_reg & (1 << 13)) >> 13) << 8);
+			((phy_reg & (0x1 << 13)) >> 13) << 8);
 
 	/* Set duplex depend on phy */
 	clrsetbits_le32(&regs->mac_ctl1, 1 << 0,
-			((phy_reg & (1 << 8)) >> 8) << 0);
+			((phy_reg & (0x1 << 8)) >> 8) << 0);
 
 	/* Enable RX/TX */
 	setbits_le32(&regs->ctl, 0x7);
@@ -369,15 +362,15 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 	return 0;
 }
 
-static void sunxi_wemac_eth_halt(struct eth_device *dev)
+static void sunxi_emac_eth_halt(struct eth_device *dev)
 {
 	/* Nothing to do here */
 }
 
-static int sunxi_wemac_eth_recv(struct eth_device *dev)
+static int sunxi_emac_eth_recv(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-	struct wemac_rxhdr rxhdr;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+	struct emac_rxhdr rxhdr;
 	u32 rxcount;
 	u32 reg_val;
 	int rx_len;
@@ -386,8 +379,7 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 
 	/* Check packet ready or not */
 
-	/*
-	 * Race warning: The first packet might arrive with
+	/* Race warning: The first packet might arrive with
 	 * the interrupts disabled, but the second will fix
 	 */
 	rxcount = readl(&regs->rx_fbc);
@@ -401,26 +393,25 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 	reg_val = readl(&regs->rx_io_data);
 	if (reg_val != 0x0143414d) {
 		/* Disable RX */
-		clrbits_le32(&regs->ctl, 1 << 2);
+		clrbits_le32(&regs->ctl, 0x1 << 2);
 
 		/* Flush RX FIFO */
-		setbits_le32(&regs->rx_ctl, 1 << 3);
-		while (readl(&regs->rx_ctl) & (1 << 3))
+		setbits_le32(&regs->rx_ctl, 0x1 << 3);
+		while (readl(&regs->rx_ctl) & (0x1 << 3))
 			;
 
 		/* Enable RX */
-		setbits_le32(&regs->ctl, 1 << 2);
+		setbits_le32(&regs->ctl, 0x1 << 2);
 
 		return 0;
 	}
 
-	/*
-	 * A packet ready now
+	/* A packet ready now
 	 * Get status/length
 	 */
 	good_packet = 1;
 
-	wemac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
+	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
 
 	rx_len = rxhdr.rx_len;
 	rx_status = rxhdr.rx_status;
@@ -440,13 +431,13 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 			printf("length error\n");
 	}
 
-	/* Move data from WEMAC */
+	/* Move data from EMAC */
 	if (good_packet) {
 		if (rx_len > DMA_CPU_TRRESHOLD) {
 			printf("Received packet is too big (len=%d)\n", rx_len);
 		} else {
-			wemac_inblk_32bit((void *)&regs->rx_io_data,
-					  NetRxPackets[0], rx_len);
+			emac_inblk_32bit((void *)&regs->rx_io_data,
+					 NetRxPackets[0], rx_len);
 
 			/* Pass to upper layer */
 			NetReceive(NetRxPackets[0], rx_len);
@@ -457,15 +448,15 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 	return 0;
 }
 
-static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
+static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* Select channel 0 */
 	writel(0, &regs->tx_ins);
 
 	/* Write packet */
-	wemac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
+	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
 
 	/* Set TX len */
 	writel(len, &regs->tx_pl0);
@@ -476,50 +467,55 @@ static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
 	return 0;
 }
 
-int sunxi_wemac_initialize(void)
+int sunxi_emac_initialize(void)
 {
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
+	struct emac_regs *regs =
+		(struct emac_regs *)SUNXI_EMAC_BASE;
 	struct eth_device *dev;
-	struct wemac_eth_dev *priv;
+	struct emac_eth_dev *priv;
 	int pin;
 
 	dev = malloc(sizeof(*dev));
 	if (dev == NULL)
 		return -ENOMEM;
 
-	priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
+	priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
 	if (!priv) {
 		free(dev);
 		return -ENOMEM;
 	}
 
 	memset(dev, 0, sizeof(*dev));
-	memset(priv, 0, sizeof(struct wemac_eth_dev));
+	memset(priv, 0, sizeof(struct emac_eth_dev));
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);
 
 	/* Configure pin mux settings for MII Ethernet */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, 2);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
 
 	/* Set up clock gating */
-	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
+	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+
+	/* Set MII clock */
+	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
 
-	dev->iobase = SUNXI_EMAC_BASE;
+	dev->iobase = (int)regs;
 	dev->priv = priv;
-	dev->init = sunxi_wemac_eth_init;
-	dev->halt = sunxi_wemac_eth_halt;
-	dev->send = sunxi_wemac_eth_send;
-	dev->recv = sunxi_wemac_eth_recv;
-	strcpy(dev->name, "wemac");
+	dev->init = sunxi_emac_eth_init;
+	dev->halt = sunxi_emac_eth_halt;
+	dev->send = sunxi_emac_eth_send;
+	dev->recv = sunxi_emac_eth_recv;
+	strcpy(dev->name, "emac");
 
 	eth_register(dev);
 
-	miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
+	miiphy_register(dev->name, emac_phy_read, emac_phy_write);
 
 	return 0;
 }
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 53ff97d745..dc64e4d32b 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -5,6 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_AXP152_POWER)	+= axp152.o
+obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c
new file mode 100644
index 0000000000..fa4ea050a5
--- /dev/null
+++ b/drivers/power/axp152.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <axp152.h>
+
+enum axp152_reg {
+	AXP152_CHIP_VERSION = 0x3,
+	AXP152_DCDC2_VOLTAGE = 0x23,
+	AXP152_DCDC3_VOLTAGE = 0x27,
+	AXP152_DCDC4_VOLTAGE = 0x2B,
+	AXP152_LDO2_VOLTAGE = 0x2A,
+	AXP152_SHUTDOWN = 0x32,
+};
+
+#define AXP152_POWEROFF			(1 << 7)
+
+static int axp152_write(enum axp152_reg reg, u8 val)
+{
+	return i2c_write(0x30, reg, 1, &val, 1);
+}
+
+static int axp152_read(enum axp152_reg reg, u8 *val)
+{
+	return i2c_read(0x30, reg, 1, val, 1);
+}
+
+static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return (mvolt - min) / div;
+}
+
+int axp152_set_dcdc2(int mvolt)
+{
+	int rc;
+	u8 current, target;
+
+	target = axp152_mvolt_to_target(mvolt, 700, 2275, 25);
+
+	/* Do we really need to be this gentle? It has built-in voltage slope */
+	while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, &current)) == 0 &&
+	       current != target) {
+		if (current < target)
+			current++;
+		else
+			current--;
+		rc = axp152_write(AXP152_DCDC2_VOLTAGE, current);
+		if (rc)
+			break;
+	}
+	return rc;
+}
+
+int axp152_set_dcdc3(int mvolt)
+{
+	u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+	return axp152_write(AXP152_DCDC3_VOLTAGE, target);
+}
+
+int axp152_set_dcdc4(int mvolt)
+{
+	u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+	return axp152_write(AXP152_DCDC4_VOLTAGE, target);
+}
+
+int axp152_set_ldo2(int mvolt)
+{
+	u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100);
+
+	return axp152_write(AXP152_LDO2_VOLTAGE, target);
+}
+
+int axp152_init(void)
+{
+	u8 ver;
+	int rc;
+
+	rc = axp152_read(AXP152_CHIP_VERSION, &ver);
+	if (rc)
+		return rc;
+
+	if (ver != 0x05)
+		return -1;
+
+	return 0;
+}
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
new file mode 100644
index 0000000000..9798e5bf7c
--- /dev/null
+++ b/drivers/power/axp209.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <axp209.h>
+
+enum axp209_reg {
+	AXP209_POWER_STATUS = 0x00,
+	AXP209_CHIP_VERSION = 0x03,
+	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_DCDC3_VOLTAGE = 0x27,
+	AXP209_LDO24_VOLTAGE = 0x28,
+	AXP209_LDO3_VOLTAGE = 0x29,
+	AXP209_IRQ_STATUS5 = 0x4c,
+	AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC	(1 << 0)
+
+#define AXP209_IRQ5_PEK_UP		(1 << 6)
+#define AXP209_IRQ5_PEK_DOWN		(1 << 5)
+
+#define AXP209_POWEROFF			(1 << 7)
+
+static int axp209_write(enum axp209_reg reg, u8 val)
+{
+	return i2c_write(0x34, reg, 1, &val, 1);
+}
+
+static int axp209_read(enum axp209_reg reg, u8 *val)
+{
+	return i2c_read(0x34, reg, 1, val, 1);
+}
+
+static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return (mvolt - min) / div;
+}
+
+int axp209_set_dcdc2(int mvolt)
+{
+	int rc;
+	u8 cfg, current;
+
+	cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+	/* Do we really need to be this gentle? It has built-in voltage slope */
+	while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, &current)) == 0 &&
+	       current != cfg) {
+		if (current < cfg)
+			current++;
+		else
+			current--;
+
+		rc = axp209_write(AXP209_DCDC2_VOLTAGE, current);
+		if (rc)
+			break;
+	}
+
+	return rc;
+}
+
+int axp209_set_dcdc3(int mvolt)
+{
+	u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
+
+	return axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo2(int mvolt)
+{
+	int rc;
+	u8 cfg, reg;
+
+	cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
+
+	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
+	if (rc)
+		return rc;
+
+	/* LDO2 configuration is in upper 4 bits */
+	reg = (reg & 0x0f) | (cfg << 4);
+	return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+int axp209_set_ldo3(int mvolt)
+{
+	u8 cfg;
+
+	if (mvolt == -1)
+		cfg = 0x80;	/* determined by LDO3IN pin */
+	else
+		cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+	return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo4(int mvolt)
+{
+	int rc;
+	static const int vindex[] = {
+		1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
+		2700, 2800, 3000, 3100, 3200, 3300
+	};
+	u8 cfg, reg;
+
+	/* Translate mvolt to register cfg value, requested <= selected */
+	for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
+
+	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
+	if (rc)
+		return rc;
+
+	/* LDO4 configuration is in lower 4 bits */
+	reg = (reg & 0xf0) | (cfg << 0);
+	return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+int axp209_init(void)
+{
+	u8 ver;
+	int rc;
+
+	rc = axp209_read(AXP209_CHIP_VERSION, &ver);
+	if (rc)
+		return rc;
+
+	/* Low 4 bits is chip version */
+	ver &= 0x0f;
+
+	if (ver != 0x1)
+		return -1;
+
+	return 0;
+}
+
+int axp209_poweron_by_dc(void)
+{
+	u8 v;
+
+	if (axp209_read(AXP209_POWER_STATUS, &v))
+		return 0;
+
+	return (v & AXP209_POWER_STATUS_ON_BY_DC);
+}
+
+int axp209_power_button(void)
+{
+	u8 v;
+
+	if (axp209_read(AXP209_IRQ_STATUS5, &v))
+		return 0;
+
+	axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
+
+	return v & AXP209_IRQ5_PEK_DOWN;
+}
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index 0952456379..dbc7a73a72 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -7,6 +7,8 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <asm/errno.h>
+#include <power/pmic.h>
 #include <power/tps65218.h>
 
 /**
@@ -95,3 +97,23 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
 
 	return 0;
 }
+
+int power_tps65218_init(unsigned char bus)
+{
+	static const char name[] = "TPS65218_PMIC";
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = TPS65218_PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = TPS65218_CHIP_PM;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f26979dbe1..8e7052dda7 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -30,7 +30,7 @@
 #define serial_in(y)		readb(y)
 #endif
 
-#if defined(CONFIG_K2HK_EVM)
+#if defined(CONFIG_SOC_KEYSTONE)
 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE   0
 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
 #undef UART_MCRVAL
@@ -88,7 +88,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	/* /16 is proper to hit 115200 with 48MHz */
 	serial_out(0, &com_port->mdr1);
 #endif /* CONFIG_OMAP */
-#if defined(CONFIG_K2HK_EVM)
+#if defined(CONFIG_SOC_KEYSTONE)
 	serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
 #endif
 }
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index fd61a5e545..d2eb7520d0 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -254,6 +254,48 @@ void serial_initialize(void)
 	serial_assign(default_serial_console()->name);
 }
 
+int serial_stub_start(struct stdio_dev *sdev)
+{
+	struct serial_device *dev = sdev->priv;
+
+	return dev->start();
+}
+
+int serial_stub_stop(struct stdio_dev *sdev)
+{
+	struct serial_device *dev = sdev->priv;
+
+	return dev->stop();
+}
+
+void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+{
+	struct serial_device *dev = sdev->priv;
+
+	dev->putc(ch);
+}
+
+void serial_stub_puts(struct stdio_dev *sdev, const char *str)
+{
+	struct serial_device *dev = sdev->priv;
+
+	dev->puts(str);
+}
+
+int serial_stub_getc(struct stdio_dev *sdev)
+{
+	struct serial_device *dev = sdev->priv;
+
+	return dev->getc();
+}
+
+int serial_stub_tstc(struct stdio_dev *sdev)
+{
+	struct serial_device *dev = sdev->priv;
+
+	return dev->tstc();
+}
+
 /**
  * serial_stdio_init() - Register serial ports with STDIO core
  *
@@ -272,12 +314,12 @@ void serial_stdio_init(void)
 		strcpy(dev.name, s->name);
 		dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
 
-		dev.start = s->start;
-		dev.stop = s->stop;
-		dev.putc = s->putc;
-		dev.puts = s->puts;
-		dev.getc = s->getc;
-		dev.tstc = s->tstc;
+		dev.start = serial_stub_start;
+		dev.stop = serial_stub_stop;
+		dev.putc = serial_stub_putc;
+		dev.puts = serial_stub_puts;
+		dev.getc = serial_stub_getc;
+		dev.tstc = serial_stub_tstc;
 
 		stdio_register(&dev);
 
@@ -376,6 +418,7 @@ static struct serial_device *get_current(void)
  */
 int serial_init(void)
 {
+	gd->flags |= GD_FLG_SERIAL_READY;
 	return get_current()->start();
 }
 
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index ba68d46948..4413e69118 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -120,6 +120,8 @@ static NS16550_t serial_ports[6] = {
 
 static int calc_divisor (NS16550_t port)
 {
+	const unsigned int mode_x_div = 16;
+
 #ifdef CONFIG_OMAP1510
 	/* If can't cleanly clock 115200 set div to 1 */
 	if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
@@ -128,21 +130,9 @@ static int calc_divisor (NS16550_t port)
 	}
 	port->osc_12m_sel = 0;			/* clear if previsouly set */
 #endif
-#ifdef CONFIG_OMAP1610
-	/* If can't cleanly clock 115200 set div to 1 */
-	if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
-		return (26);		/* return 26 for base divisor */
-	}
-#endif
 
-#define MODE_X_DIV 16
-	/* Compute divisor value. Normally, we should simply return:
-	 *   CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
-	 * but we need to round that value by adding 0.5.
-	 * Rounding is especially important at high baud rates.
-	 */
-	return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
-		(MODE_X_DIV * gd->baudrate);
+	return DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK,
+						mode_x_div * gd->baudrate);
 }
 
 void
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index f5e9854d13..341997c8ec 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -226,7 +226,8 @@ struct uart_port {
 # define SCSPTR3 0xffc60020		/* 16 bit SCIF */
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+	defined(CONFIG_R8A7794)
 # define SCIF_ORER	0x0001
 # define SCSCR_INIT(port)	0x32	/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 6b912efafd..b030526b6a 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -389,7 +389,7 @@ static void str2wide (char *str, u16 * wide)
  * Test whether a character is in the RX buffer
  */
 
-int usbtty_tstc (void)
+int usbtty_tstc(struct stdio_dev *dev)
 {
 	struct usb_endpoint_instance *endpoint =
 		&endpoint_instance[rx_endpoint];
@@ -409,7 +409,7 @@ int usbtty_tstc (void)
  * written into its argument c.
  */
 
-int usbtty_getc (void)
+int usbtty_getc(struct stdio_dev *dev)
 {
 	char c;
 	struct usb_endpoint_instance *endpoint =
@@ -429,7 +429,7 @@ int usbtty_getc (void)
 /*
  * Output a single byte to the usb client port.
  */
-void usbtty_putc (const char c)
+void usbtty_putc(struct stdio_dev *dev, const char c)
 {
 	if (!usbtty_configured ())
 		return;
@@ -484,7 +484,7 @@ static void __usbtty_puts (const char *str, int len)
 	}
 }
 
-void usbtty_puts (const char *str)
+void usbtty_puts(struct stdio_dev *dev, const char *str)
 {
 	int n;
 	int len;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index ceb1573d86..6685ed23de 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -20,9 +20,7 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <linux/list.h>
-
-#define upper_32_bits(n) (u32)((n) >> 32)
-#define lower_32_bits(n) (u32)(n)
+#include <linux/compat.h>
 
 #define MAX_EP_CTX_NUM		31
 #define XHCI_ALIGNMENT		64
@@ -1121,7 +1119,7 @@ static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
 	__u32 *ptr = (__u32 *)regs;
 	u32 val_lo = lower_32_bits(val);
 	/* FIXME */
-	u32 val_hi = 0;
+	u32 val_hi = upper_32_bits(val);
 	writel(val_lo, ptr);
 	writel(val_hi, ptr + 1);
 }
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index b52e9edd25..9231927879 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -944,7 +944,7 @@ static void parse_putc(const char c)
 		CURSOR_SET;
 }
 
-void video_putc(const char c)
+void video_putc(struct stdio_dev *dev, const char c)
 {
 #ifdef CONFIG_CFB_CONSOLE_ANSI
 	int i;
@@ -1158,12 +1158,12 @@ void video_putc(const char c)
 		flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
 }
 
-void video_puts(const char *s)
+void video_puts(struct stdio_dev *dev, const char *s)
 {
 	int count = strlen(s);
 
 	while (count--)
-		video_putc(*s++);
+		video_putc(dev, *s++);
 }
 
 /*
@@ -2279,8 +2279,6 @@ int drv_video_init(void)
 	console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
 	console_dev.putc = video_putc;	/* 'putc' function */
 	console_dev.puts = video_puts;	/* 'puts' function */
-	console_dev.tstc = NULL;	/* 'tstc' function */
-	console_dev.getc = NULL;	/* 'getc' function */
 
 #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
 	/* Also init console device */
diff --git a/fs/fs.c b/fs/fs.c
index 79d432d58f..ea15c5f447 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -276,6 +276,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 	unsigned long pos;
 	int len_read;
 	unsigned long time;
+	char *ep;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
@@ -286,7 +287,9 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		return 1;
 
 	if (argc >= 4) {
-		addr = simple_strtoul(argv[3], NULL, 16);
+		addr = simple_strtoul(argv[3], &ep, 16);
+		if (ep == argv[3] || *ep != '\0')
+			return CMD_RET_USAGE;
 	} else {
 		addr_str = getenv("loadaddr");
 		if (addr_str != NULL)
diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
index 21441fd991..32e6ff2a04 100644
--- a/fs/yaffs2/yaffs_guts.c
+++ b/fs/yaffs2/yaffs_guts.c
@@ -219,18 +219,11 @@ static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk,
 				     const u8 *data,
 				     const struct yaffs_ext_tags *tags)
 {
-	dev = dev;
-	nand_chunk = nand_chunk;
-	data = data;
-	tags = tags;
 }
 
 static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk,
 				      const struct yaffs_ext_tags *tags)
 {
-	dev = dev;
-	nand_chunk = nand_chunk;
-	tags = tags;
 }
 
 void yaffs_handle_chunk_error(struct yaffs_dev *dev,
@@ -814,8 +807,6 @@ struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev,
 	int required_depth;
 	int level = file_struct->top_level;
 
-	dev = dev;
-
 	/* Check sane level and chunk Id */
 	if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL)
 		return NULL;
@@ -3212,20 +3203,18 @@ static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR *name,
 		} else {
 			yaffs_strncpy(name, oh_name + 1, buff_size - 1);
 		}
-	} else {
-#else
-	dev = dev;
-	{
-#endif
-		yaffs_strncpy(name, oh_name, buff_size - 1);
+
+		return;
 	}
+#endif
+
+	yaffs_strncpy(name, oh_name, buff_size - 1);
 }
 
 static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name,
 				    const YCHAR *name)
 {
 #ifdef CONFIG_YAFFS_AUTO_UNICODE
-
 	int is_ascii;
 	YCHAR *w;
 
@@ -3256,13 +3245,12 @@ static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name,
 			*oh_name = 0;
 			yaffs_strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2);
 		}
-	} else {
-#else
-	dev = dev;
-	{
-#endif
-		yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1);
+
+		return;
 	}
+#endif
+
+	yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1);
 }
 
 /* UpdateObjectHeader updates the header on NAND for an object.
diff --git a/fs/yaffs2/yaffs_verify.c b/fs/yaffs2/yaffs_verify.c
index 97734a9e29..3fef28bdcb 100644
--- a/fs/yaffs2/yaffs_verify.c
+++ b/fs/yaffs2/yaffs_verify.c
@@ -19,20 +19,17 @@
 
 int yaffs_skip_verification(struct yaffs_dev *dev)
 {
-	dev = dev;
 	return !(yaffs_trace_mask &
 		 (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
 }
 
 static int yaffs_skip_full_verification(struct yaffs_dev *dev)
 {
-	dev = dev;
 	return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL));
 }
 
 static int yaffs_skip_nand_verification(struct yaffs_dev *dev)
 {
-	dev = dev;
 	return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND));
 }
 
@@ -521,6 +518,5 @@ void yaffs_verify_free_chunks(struct yaffs_dev *dev)
 
 int yaffs_verify_file_sane(struct yaffs_obj *in)
 {
-	in = in;
 	return YAFFS_OK;
 }
diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c
index 334598eedf..41e5f0108c 100644
--- a/fs/yaffs2/yaffsfs.c
+++ b/fs/yaffs2/yaffsfs.c
@@ -3136,10 +3136,6 @@ int yaffs_link(const YCHAR *oldpath, const YCHAR *linkpath)
 
 int yaffs_mknod(const YCHAR *pathname, mode_t mode, dev_t dev)
 {
-	pathname = pathname;
-	mode = mode;
-	dev = dev;
-
 	yaffsfs_SetError(-EINVAL);
 	return -1;
 }
@@ -3187,9 +3183,7 @@ int yaffs_set_error(int error)
 
 int yaffs_dump_dev(const YCHAR *path)
 {
-#if 1
-	path = path;
-#else
+#if 0
 	YCHAR *rest;
 
 	struct yaffs_obj *obj = yaffsfs_FindRoot(path, &rest);
diff --git a/include/altera.h b/include/altera.h
index 0327a1b82a..ae5f7eec46 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -26,7 +26,7 @@ typedef enum {			/* typedef Altera_Family */
 	min_altera_type,	/* insert all new types after this */
 	Altera_ACEX1K,		/* ACEX1K Family */
 	Altera_CYC2,		/* CYCLONII Family */
-	Altera_StratixII,	/* StratixII Familiy */
+	Altera_StratixII,	/* StratixII Family */
 /* Add new models here */
 	max_altera_type		/* insert all new types before this */
 } Altera_Family;		/* end, typedef Altera_Family */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 2850ed8a69..74df210033 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -65,7 +65,8 @@ typedef struct global_data {
 	struct global_data *new_gd;	/* relocated global data */
 
 #ifdef CONFIG_DM
-	struct udevice	*dm_root;/* Root instance for Driver Model */
+	struct udevice	*dm_root;	/* Root instance for Driver Model */
+	struct udevice	*dm_root_f;	/* Pre-relocation root instance */
 	struct list_head uclass_root;	/* Head of core tree */
 #endif
 
@@ -85,6 +86,11 @@ typedef struct global_data {
 #endif
 	unsigned long timebase_h;
 	unsigned long timebase_l;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	unsigned long malloc_base;	/* base address of early malloc() */
+	unsigned long malloc_limit;	/* limit address */
+	unsigned long malloc_ptr;	/* current address */
+#endif
 	struct arch_global_data arch;	/* architecture-specific data */
 } gd_t;
 #endif
@@ -100,5 +106,6 @@ typedef struct global_data {
 #define GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
 #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	   */
 #define GD_FLG_ENV_READY	0x00080	/* Env. imported into hash table   */
+#define GD_FLG_SERIAL_READY	0x00100	/* Pre-reloc serial console ready  */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/axp152.h b/include/axp152.h
new file mode 100644
index 0000000000..3e5ccbd0d8
--- /dev/null
+++ b/include/axp152.h
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+int axp152_set_dcdc2(int mvolt);
+int axp152_set_dcdc3(int mvolt);
+int axp152_set_dcdc4(int mvolt);
+int axp152_set_ldo2(int mvolt);
+int axp152_init(void);
diff --git a/include/axp209.h b/include/axp209.h
new file mode 100644
index 0000000000..21efce64bb
--- /dev/null
+++ b/include/axp209.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+extern int axp209_set_dcdc2(int mvolt);
+extern int axp209_set_dcdc3(int mvolt);
+extern int axp209_set_ldo2(int mvolt);
+extern int axp209_set_ldo3(int mvolt);
+extern int axp209_set_ldo4(int mvolt);
+extern int axp209_init(void);
+extern int axp209_poweron_by_dc(void);
+extern int axp209_power_button(void);
diff --git a/include/common.h b/include/common.h
index 82c0a5a9a6..1d6cb48ff0 100644
--- a/include/common.h
+++ b/include/common.h
@@ -318,14 +318,14 @@ int arch_early_init_r(void);
 void board_show_dram(ulong size);
 
 /**
- * arch_fixup_memory_node() - Write arch-specific memory information to fdt
+ * arch_fixup_fdt() - Write arch-specific information to fdt
  *
- * Defined in arch/$(ARCH)/lib/bootm.c
+ * Defined in arch/$(ARCH)/lib/bootm-fdt.c
  *
  * @blob:	FDT blob to write to
  * @return 0 if ok, or -ve FDT_ERR_... on failure
  */
-int arch_fixup_memory_node(void *blob);
+int arch_fixup_fdt(void *blob);
 
 /* common/flash.c */
 void flash_perror (int);
@@ -639,6 +639,11 @@ void	serial_puts   (const char *);
 int	serial_getc   (void);
 int	serial_tstc   (void);
 
+/* These versions take a stdio_dev pointer */
+struct stdio_dev;
+int serial_stub_getc(struct stdio_dev *sdev);
+int serial_stub_tstc(struct stdio_dev *sdev);
+
 void	_serial_setbrg (const int);
 void	_serial_putc   (const char, const int);
 void	_serial_putc_raw(const char, const int);
diff --git a/include/compiler.h b/include/compiler.h
index 0734ed4942..9afc11be19 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -48,6 +48,7 @@
 # include <machine/endian.h>
 typedef unsigned long ulong;
 #endif
+#include <time.h>
 
 typedef uint8_t __u8;
 typedef uint16_t __u16;
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 0ffbd41b49..debfc3697e 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -234,8 +234,8 @@
 #define CONFIG_VIDEO
 #define CONFIG_CFB_CONSOLE
 #define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
-#define VIDEO_TSTC_FCT        serial_tstc
-#define VIDEO_GETC_FCT        serial_getc
+#define VIDEO_TSTC_FCT		serial_stub_tstc
+#define VIDEO_GETC_FCT		serial_stub_getc
 
 #define CONFIG_VIDEO_SMI_LYNXEM
 #define CONFIG_VIDEO_LOGO
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 6314b5380d..d45be0f609 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -96,8 +96,8 @@
 #define CONFIG_VIDEO_LOGO
 
 #define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT		serial_tstc
-#define VIDEO_GETC_FCT		serial_getc
+#define VIDEO_TSTC_FCT		serial_stub_tstc
+#define VIDEO_GETC_FCT		serial_stub_getc
 
 #define CONFIG_BR0_WORKAROUND	1
 
diff --git a/include/configs/alt.h b/include/configs/alt.h
new file mode 100644
index 0000000000..9eec4bc231
--- /dev/null
+++ b/include/configs/alt.h
@@ -0,0 +1,166 @@
+/*
+ * include/configs/alt.h
+ *     This file is alt board configuration.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ALT_H
+#define __ALT_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7794
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Alt"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+#define CONFIG_SYS_TEXT_BASE	0xE6304000
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_TMU_TIMER
+
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
+#define STACK_AREA_SIZE			0xC000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ALT_SDRAM_BASE		0x40000000
+#define ALT_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define ALT_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(ALT_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(ALT_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(ALT_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		0xC0000
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_low=0x40e00000\0" \
+	"bootm_size=0x100000\0" \
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK        20000000u
+#define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV  4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
+#define CONFIG_SYS_I2C_SH_BASE0		0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SYS_I2C_SH_BASE1		0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1	400000
+#define CONFIG_SYS_I2C_SH_BASE2		0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2	400000
+#define CONFIG_SH_I2C_DATA_HIGH		4
+#define CONFIG_SH_I2C_DATA_LOW		5
+#define CONFIG_SH_I2C_CLOCK		10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+#endif /* __ALT_H */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a48b386477..35ae0e6fb7 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -117,7 +117,7 @@
 	"bootenv=uEnv.txt\0" \
 	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t $loadaddr $filesize\0" \
+		"env import -t -r $loadaddr $filesize\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${ramroot} " \
@@ -254,6 +254,11 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS	0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 #endif
 #endif
 
@@ -453,6 +458,7 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_FLASH_BASE		(0x08000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 /* Reduce SPL size by removing unlikey targets */
 #ifdef CONFIG_NOR_BOOT
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index ad4cbd88b8..d826214efe 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -252,17 +252,12 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
 						/* on one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 0102ff5b7f..a9c5a8f3af 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -259,18 +259,13 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
 						/* on one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 /* Monitor at start of flash */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 974ce986e9..e26204025f 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -33,6 +33,8 @@
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 
 /* Power */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
 #define CONFIG_POWER_TPS65218
 
 /* SPL defines. */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 4d1dd28a91..a3e6452ec1 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -150,6 +150,11 @@
 #define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #define CONFIG_SYS_NAND_ONFI_DETECTION
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x400000 /* un-assigned: (using dtb) */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x500000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 /* GPIO pin + bank to pin ID mapping */
 #define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 5c484ef078..d8d71a94ee 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -258,9 +258,6 @@
  */
 
 /* **** PISMO SUPPORT *** */
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 5308790fe6..cc53fc9cd7 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -262,8 +262,6 @@
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
 
 /* NAND and environment organization  */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_ENV_IS_IN_NAND		1
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index ce205e9b3e..7e47c56453 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -251,10 +251,6 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_FLASH_BASE		boot_flash_base
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 8b9f66a29c..77717a84ae 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -187,7 +187,8 @@
  * I2C related stuff
  */
 #ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_I2C_MVTWSI_BASE		ORION5X_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 5d0b85e431..9470ad6abc 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -123,6 +123,7 @@
 #define CONFIG_CMD_IMI
 
 #define CONFIG_FIT
+#define CONFIG_FIT_DISABLE_SHA256
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index b34e3422da..759e1129c2 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -87,8 +87,8 @@
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (800*480 + 256*4 + 10*1024)
 #define VIDEO_FB_16BPP_WORD_SWAP
 #define VIDEO_KBD_INIT_FCT		0
-#define VIDEO_TSTC_FCT			serial_tstc
-#define VIDEO_GETC_FCT			serial_getc
+#define VIDEO_TSTC_FCT		serial_stub_tstc
+#define VIDEO_GETC_FCT		serial_stub_getc
 
 /*
  * BOOTP options
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
new file mode 100644
index 0000000000..3502d10472
--- /dev/null
+++ b/include/configs/k2e_evm.h
@@ -0,0 +1,37 @@
+/*
+ * Configuration header file for TI's k2e-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2E_EVM_H
+#define __CONFIG_K2E_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2E
+#define CONFIG_K2E_EVM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT               "K2E EVM # "
+
+#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
+
+#define KS2_FDT_NAME   "name_fdt=k2e-evm.dtb\0"
+#define KS2_ADDR_MON   "addr_mon=0x0c140000\0"
+#define KS2_NAME_MON   "name_mon=skern-k2e-evm.bin\0"
+#define NAME_UBOOT     "name_uboot=u-boot-spi-k2e-evm.gph\0"
+#define NAME_UBI       "name_ubi=k2e-evm-ubifs.ubi\0"
+
+#include <configs/ks2_evm.h>
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE           0x0c100000
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#endif /* __CONFIG_K2E_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 858329f958..8aa616da0e 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -14,252 +14,27 @@
 #define CONFIG_SOC_K2HK
 #define CONFIG_K2HK_EVM
 
-/* U-Boot Build Configuration */
-#define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is a 2nd stage loader */
-#define CONFIG_SYS_NO_FLASH             /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_THUMB_BUILD
-
-/* SoC Configuration */
-#define CONFIG_ARMV7
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ                   1000
-#define CONFIG_SYS_TEXT_BASE            0x0c001000
-#define CONFIG_SPL_TARGET               "u-boot-spi.gph"
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Memory Configuration */
-#define CONFIG_NR_DRAM_BANKS            2
-#define CONFIG_SYS_SDRAM_BASE           0x80000000
-#define CONFIG_SYS_LPAE_SDRAM_BASE      0x800000000
-#define CONFIG_MAX_RAM_BANK_SIZE        (2 << 30)       /* 2GB */
-#define CONFIG_STACKSIZE                (512 << 10)     /* 512 KiB */
-#define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* 4 MiB */
-#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-/* SPL SPI Loader Configuration */
-#define CONFIG_SPL_TEXT_BASE            0x0c200000
-#define CONFIG_SPL_PAD_TO               65536
-#define CONFIG_SPL_MAX_SIZE             (CONFIG_SPL_PAD_TO - 8)
-#define CONFIG_SPL_BSS_START_ADDR       (CONFIG_SPL_TEXT_BASE + \
-					 CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SPL_BSS_MAX_SIZE         (32 * 1024)
-#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
-					 CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE      (32 * 1024)
-#define CONFIG_SPL_STACK_SIZE           (8 * 1024)
-#define CONFIG_SPL_STACK                (CONFIG_SYS_SPL_MALLOC_START + \
-					 CONFIG_SYS_SPL_MALLOC_SIZE + \
-					 CONFIG_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS              0
-#define CONFIG_SPL_SPI_CS               0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS      CONFIG_SPL_PAD_TO
-#define CONFIG_SPL_FRAMEWORK
-
-/* UART Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_REG_SIZE     -4
-#define CONFIG_SYS_NS16550_COM1         KS2_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2         KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK          clk_get_rate(K2HK_CLK1_6)
-#define CONFIG_CONS_INDEX               1
-#define CONFIG_BAUDRATE                 115200
-
-/* SPI Configuration */
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI0
-#define CONFIG_SYS_SPI_BASE             K2HK_SPI_BASE
-#define CONFIG_SYS_SPI0_NUM_CS          4
-#define CONFIG_SYS_SPI1
-#define CONFIG_SYS_SPI1_BASE            K2HK_SPI1_BASE
-#define CONFIG_SYS_SPI1_NUM_CS          4
-#define CONFIG_SYS_SPI2
-#define CONFIG_SYS_SPI2_NUM_CS          4
-#define CONFIG_SYS_SPI2_BASE            K2HK_SPI2_BASE
-#define CONFIG_CMD_SPI
-#define CONFIG_SYS_SPI_CLK              clk_get_rate(K2HK_LPSC_EMIF25_SPI)
-#define CONFIG_SF_DEFAULT_SPEED         30000000
-#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT               "K2HK EVM # "
 
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED    100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE    0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED1   100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE1   0x10 /* SMBus host address */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED2   100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE2   0x10 /* SMBus host address */
-#define I2C_BUS_MAX                     3
+#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
 
-/* EEPROM definitions */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
-#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  20
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define KS2_FDT_NAME   "name_fdt=k2hk-evm.dtb\0"
+#define KS2_ADDR_MON   "addr_mon=0x0c5f0000\0"
+#define KS2_NAME_MON   "name_mon=skern-k2hk-evm.bin\0"
+#define NAME_UBOOT     "name_uboot=u-boot-spi-k2hk-evm.gph\0"
+#define NAME_UBI       "name_ubi=k2hk-evm-ubifs.ubi\0"
 
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT                 32
-#define CONFIG_NET_MULTI
-#define CONFIG_GET_LINK_STATUS_ATTEMPTS        5
-#define CONFIG_SYS_SGMII_REFCLK_MHZ            312
-#define CONFIG_SYS_SGMII_LINERATE_MHZ          1250
-#define CONFIG_SYS_SGMII_RATESCALE             2
+#include <configs/ks2_evm.h>
 
-/* AEMIF */
-#define CONFIG_TI_AEMIF
-#define CONFIG_AEMIF_CNTRL_BASE		       KS2_AEMIF_CNTRL_BASE
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE		0x0c200000
 
 /* NAND Configuration */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_NAND_ECCLAYOUT
-#define CONFIG_SYS_NAND_CS                     2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_MASK_CLE		0x4000
-#define CONFIG_SYS_NAND_MASK_ALE		0x2000
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST       { 0x30000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE      1
-#define CONFIG_SYS_NAND_MAX_CHIPS       1
-#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-#define CONFIG_ENV_SIZE                 (256 << 10)  /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET               0x100000
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define MTDPARTS_DEFAULT                "mtdparts=davinci_nand.0:" \
-					"1024k(bootloader)ro,512k(params)ro," \
-					"-(ubifs)"
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_EEPROM
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SYS_PROMPT               "K2HK EVM # "
-#define CONFIG_SYS_CBSIZE               1024
-#define CONFIG_SYS_PBSIZE		2048
-#define CONFIG_SYS_MAXARGS              16
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
 
-#define CONFIG_BOOTDELAY                3
-#define CONFIG_BOOTFILE                 "uImage"
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"boot=ramfs\0"							\
-	"tftp_root=/\0"							\
-	"nfs_root=/export\0"						\
-	"mem_lpae=1\0"							\
-	"mem_reserve=512M\0"						\
-	"addr_fdt=0x87000000\0"						\
-	"addr_kern=0x88000000\0"					\
-	"addr_mon=0x0c5f0000\0"						\
-	"addr_uboot=0x87000000\0"					\
-	"addr_fs=0x82000000\0"						\
-	"addr_ubi=0x82000000\0"						\
-	"fdt_high=0xffffffff\0"						\
-	"name_fdt=uImage-k2hk-evm.dtb\0"				\
-	"name_fs=arago-console-image.cpio.gz\0"				\
-	"name_kern=uImage-keystone-evm.bin\0"				\
-	"name_mon=skern-keystone-evm.bin\0"				\
-	"name_uboot=u-boot-spi-keystone-evm.gph\0"			\
-	"name_ubi=keystone-evm-ubifs.ubi\0"				\
-	"run_mon=mon_install ${addr_mon}\0"				\
-	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
-	"init_net=run args_all args_net\0"				\
-	"init_ubi=run args_all args_ubi; "				\
-		"ubi part ubifs; ubifsmount boot\0"			\
-	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
-	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
-	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
-	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0"		\
-	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
-	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
-	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0"	\
-	"burn_uboot=sf probe; sf erase 0 0x100000; "			\
-		"sf write ${addr_uboot} 0 ${filesize}\0"		\
-	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
-	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-		"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"	\
-	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
-		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
-		"${nfs_options} ip=dhcp\0"				\
-	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
-	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
-	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
-	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
-	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0"	\
-	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
-	"burn_ubi=nand erase.part ubifs; "				\
-		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
-	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
-	"args_ramfs=setenv bootargs ${bootargs} earlyprintk "		\
-		"rdinit=/sbin/init rw root=/dev/ram0 "			\
-		"initrd=0x802000000,9M\0"				\
-	"no_post=1\0"							\
-	"mtdparts=mtdparts=davinci_nand.0:"				\
-		"1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0"
-#define CONFIG_BOOTCOMMAND						\
-	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
-		"get_kern_${boot} run_mon run_kern"
-#define CONFIG_BOOTARGS							\
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_OF_LIBFDT                1
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_SYS_BARGSIZE             1024
-#define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x08000000)
-
-#define CONFIG_SUPPORT_RAW_INITRD
-
-/* we may include files below only after all above definitions */
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#define CONFIG_SYS_HZ_CLOCK             clk_get_rate(K2HK_CLK1_6)
+/* Network */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
 
 #endif /* __CONFIG_K2HK_EVM_H */
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
new file mode 100644
index 0000000000..43db581c75
--- /dev/null
+++ b/include/configs/ks2_evm.h
@@ -0,0 +1,275 @@
+/*
+ * Common configuration header file for all Keystone II EVM platforms
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_KS2_EVM_H
+#define __CONFIG_KS2_EVM_H
+
+#define CONFIG_SOC_KEYSTONE
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_THUMB_BUILD
+
+/* SoC Configuration */
+#define CONFIG_ARMV7
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_TEXT_BASE		0x0c001000
+#define CONFIG_SPL_TARGET		"u-boot-spi.gph"
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
+#define CONFIG_STACKSIZE		(512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)       /* 4 MiB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_PAD_TO		65536
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SPL_TEXT_BASE + \
+					CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
+#define CONFIG_SPL_STACK_SIZE		(8 * 1024)
+#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
+					CONFIG_SYS_SPL_MALLOC_SIZE + \
+					CONFIG_SPL_STACK_SIZE - 4)
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SPL_FRAMEWORK
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
+#define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* SPI Configuration */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_SPI_CLK		clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
+#define CONFIG_SYS_SPI0_NUM_CS		4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS		4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
+#define CONFIG_SYS_SPI2_NUM_CS		4
+
+/* Network Configuration */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		32
+#define CONFIG_NET_MULTI
+#define CONFIG_GET_LINK_STATUS_ATTEMPTS	5
+#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
+#define CONFIG_SYS_SGMII_RATESCALE	2
+
+/* AEMIF */
+#define CONFIG_TI_AEMIF
+#define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
+#define I2C_BUS_MAX			3
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* NAND Configuration */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_KEYSTONE_RBL_NAND
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
+#define CONFIG_SYS_NAND_MASK_CLE		0x4000
+#define CONFIG_SYS_NAND_MASK_ALE		0x2000
+#define CONFIG_SYS_NAND_CS			2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET			0x100000
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:" \
+					"1024k(bootloader)ro,512k(params)ro," \
+					"-(ubifs)"
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_EEPROM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		2048
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* EDMA3 */
+#define CONFIG_TI_EDMA3
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"boot=ramfs\0"							\
+	"tftp_root=/\0"							\
+	"nfs_root=/export\0"						\
+	"mem_lpae=1\0"							\
+	"mem_reserve=512M\0"						\
+	"addr_fdt=0x87000000\0"						\
+	"addr_kern=0x88000000\0"					\
+	KS2_ADDR_MON							\
+	"addr_uboot=0x87000000\0"					\
+	"addr_fs=0x82000000\0"						\
+	"addr_ubi=0x82000000\0"						\
+	"addr_secdb_key=0xc000000\0"					\
+	"fdt_high=0xffffffff\0"						\
+	KS2_FDT_NAME							\
+	"name_fs=arago-console-image.cpio.gz\0"				\
+	"name_kern=uImage\0"						\
+	KS2_NAME_MON							\
+	NAME_UBOOT							\
+	NAME_UBI							\
+	"run_mon=mon_install ${addr_mon}\0"				\
+	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
+	"init_net=run args_all args_net\0"				\
+	"init_ubi=run args_all args_ubi; "				\
+		"ubi part ubifs; ubifsmount boot;"			\
+		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
+	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
+	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
+	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
+	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0"		\
+	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
+	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0"	\
+	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
+		"sf write ${addr_uboot} 0 ${filesize}\0"		\
+	"burn_uboot_nand=nand erase 0 0x100000; "			\
+		"nand write ${addr_uboot} 0 ${filesize}\0"		\
+	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
+	KS2_ARGS_UBI							\
+	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
+		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
+		"${nfs_options} ip=dhcp\0"				\
+	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
+	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
+	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
+	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0"	\
+	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
+	"burn_ubi=nand erase.part ubifs; "				\
+		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
+	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
+	"args_ramfs=setenv bootargs ${bootargs} "			\
+		"rdinit=/sbin/init rw root=/dev/ram0 "			\
+		"initrd=0x802000000,9M\0"				\
+	"no_post=1\0"							\
+	"mtdparts=mtdparts=davinci_nand.0:"				\
+		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
+		"get_kern_${boot} run_mon run_kern"
+
+#define CONFIG_BOOTARGS							\
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_SYS_BARGSIZE		1024
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x08000000)
+#define CONFIG_LINUX_BOOT_PARAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x100)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)
+
+/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
+   which is NOT applicable for DDR ECC test */
+#define CONFIG_MAX_UBOOT_MEM_SIZE	(4 << 20)	/* 4 MiB */
+
+#endif /* __CONFIG_KS2_EVM_H */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 47244c0034..75abb602cf 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -316,10 +316,6 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_ENV_IS_IN_NAND
 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index e0c0fac8e1..43c1617a5e 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -220,8 +220,6 @@
 
 #ifdef ONENAND_SUPPORT
 
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
@@ -263,9 +261,10 @@
 #define VIDEO_TSTC_FCT			rx51_kp_tstc
 #define VIDEO_GETC_FCT			rx51_kp_getc
 #ifndef __ASSEMBLY__
+struct stdio_dev;
 int rx51_kp_init(void);
-int rx51_kp_tstc(void);
-int rx51_kp_getc(void);
+int rx51_kp_tstc(struct stdio_dev *sdev);
+int rx51_kp_getc(struct stdio_dev *sdev);
 #endif
 
 #ifndef MTDPARTS_DEFAULT
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 3782049ee6..644e97f4c4 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -195,7 +195,7 @@
 	"bootenv=uEnv.txt\0" \
 	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
 	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t $loadaddr $filesize\0" \
+		"env import -t -r $loadaddr $filesize\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"mpurate=${mpurate} " \
@@ -266,13 +266,8 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 /* Monitor at start of flash */
@@ -309,5 +304,11 @@
 #define CONFIG_SYS_NAND_ECCBYTES	3
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index ae4ce63f67..739d392edc 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -95,9 +95,6 @@
 /*
  * PISMO support
  */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 /* Monitor at start of flash - Reserve 2 sectors */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
@@ -205,12 +202,12 @@
  * NAND / OneNAND
  */
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
+#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 #endif
 
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 79daabd6bb..006c9a9c0d 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -146,8 +146,6 @@
  */
 
 #ifdef CONFIG_BOOT_ONENAND
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
@@ -158,7 +156,6 @@
 #endif
 
 #ifdef CONFIG_NAND
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_ENV_IS_IN_NAND	        1
 #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
@@ -199,6 +196,13 @@
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	3
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 #endif
 
 #endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 8dcbba3c40..717c935d2c 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -277,16 +277,12 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #elif defined(CONFIG_CMD_ONENAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
+#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
 #endif
 
 /* Monitor at start of flash */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index f7483a0827..e66f30655d 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -173,12 +173,8 @@
 					0x01F00000) /* 31MB */
 
 /* FLASH and environment organization */
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #if defined(CONFIG_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 /* Monitor at start of flash */
@@ -220,5 +216,11 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index da67787e69..c22c1fc6aa 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -220,15 +220,10 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 /* Monitor at start of flash */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 3efe4cf815..93f4d627a1 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -70,6 +70,12 @@
 					"4m(kernel),-(fs)"
 
 #if defined(CONFIG_CMD_NAND)
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 #endif
 
@@ -165,13 +171,8 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 /* Monitor at start of flash */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 85104057a9..4684ad6852 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -159,6 +159,12 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x240000 /* un-assigned */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
 
 /*
  * USB configuration.  We enable MUSB support, both for host and for
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index ff48598dd5..60f24895e5 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -98,7 +98,7 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_PREBOOT \
 	"if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
-		"env import -t ${loadaddr} ${filesize}; " \
+		"env import -t -r ${loadaddr} ${filesize}; " \
 	"fi"
 
 #define ENV_DEVICE_SETTINGS \
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 12b69d9a24..bf2d25c871 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -68,8 +68,10 @@
 #define CONFIG_EFI_PARTITION
 
 /*
- * Size of malloc() pool, although we don't actually use this yet.
+ * Size of malloc() pool, before and after relocation
  */
+#define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
+#define CONFIG_MALLOC_F_ADDR		0x0010000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
 
 #define CONFIG_SYS_HUSH_PARSER
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
new file mode 100644
index 0000000000..037f9952f8
--- /dev/null
+++ b/include/configs/sun4i.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A10 specific configuration
+ */
+#define CONFIG_SUN4I		/* sun4i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		1008000000
+
+#define CONFIG_SYS_PROMPT		"sun4i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
new file mode 100644
index 0000000000..c6138b7cd4
--- /dev/null
+++ b/include/configs/sun5i.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A13 (sun5i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SUN5I		/* sun5i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		1008000000
+
+#define CONFIG_SYS_PROMPT		"sun5i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 9b693f7039..d9be1046b0 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -13,6 +13,7 @@
  * A20 specific configuration
  */
 #define CONFIG_SUN7I		/* sun7i SoC generation */
+#define CONFIG_CLK_FULL_SPEED		912000000
 
 #define CONFIG_SYS_PROMPT		"sun7i# "
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 5d72d62f14..845b004a27 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -70,7 +70,6 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
-#define CONFIG_MMC_SUNXI_USE_DMA
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
 
@@ -162,7 +161,31 @@
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
+/* I2C */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+#define CONFIG_CMD_I2C
+
+/* PMU */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+#define CONFIG_SPL_POWER_SUPPORT
+#endif
+
+#ifndef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX              1       /* UART0 */
+#endif
+
+/* GPIO */
+#define CONFIG_SUNXI_GPIO
+#define CONFIG_CMD_GPIO
+
+/* Ethernet support */
+#ifdef CONFIG_SUNXI_EMAC
+#define CONFIG_MII			/* MII PHY management		*/
+#endif
 
 #ifdef CONFIG_SUNXI_GMAC
 #define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
@@ -188,6 +211,8 @@
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 
+#define CONFIG_MISC_INIT_R
+
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 #endif
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 0c2f0f19c8..aa0ea162d2 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -181,10 +181,6 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_NAND
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_ENV_IS_IN_NAND
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 1b0fee9a80..9fc31bed6a 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -22,6 +22,7 @@
 
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define MACH_TYPE_OMAP3_TAO3530		2836
 
@@ -253,13 +254,8 @@
  */
 
 /* **** PISMO SUPPORT *** */
-
-/* Configure the PISMO */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
 
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 6e0bf09058..85c027c1d2 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -243,13 +243,6 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
 
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_SPL_NAND_OFS			0x240000 /* end of u-boot */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
-#endif
-
 /* spl export command */
 #define CONFIG_CMD_SPL
 #endif
@@ -275,7 +268,6 @@
 #define CONFIG_SPL_NAND_ECC
 #define CONFIG_SPL_MTD_SUPPORT
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif
 #endif /* !CONFIG_NOR_BOOT */
 
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 80985a2655..6c2f65305f 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -35,6 +35,8 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -315,8 +317,6 @@
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
 
 /* NAND and environment organization  */
-#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
-
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index fa252c0b13..690cacbc94 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -339,4 +339,6 @@
 
 #define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #endif /* __CONFIG_ZYNQ_COMMON_H */
diff --git a/include/cpsw.h b/include/cpsw.h
index a73843d2f7..547b40c57b 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -44,6 +44,7 @@ struct cpsw_platform_data {
 	struct cpsw_slave_data	*slave_data;
 	void	(*control)(int enabled);
 	u32	host_port_num;
+	u32	active_slave;
 	u8	version;
 };
 
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index 26e5cf530e..7005d03d08 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -45,12 +45,14 @@ int device_bind(struct udevice *parent, struct driver *drv,
  * tree.
  *
  * @parent: Pointer to device's parent
+ * @pre_reloc_only: If true, bind the driver only if its DM_INIT_F flag is set.
+ * If false bind the driver always.
  * @info: Name and platdata for this device
  * @devp: Returns a pointer to the bound device
  * @return 0 if OK, -ve on error
  */
-int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
-			struct udevice **devp);
+int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
+			const struct driver_info *info, struct udevice **devp);
 
 /**
  * device_probe() - Probe a device, activating it
diff --git a/include/dm/device.h b/include/dm/device.h
index ae75a3f54d..c8a4072bcf 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -23,6 +23,9 @@ struct driver_info;
 /* DM is responsible for allocating and freeing platdata */
 #define DM_FLAG_ALLOC_PDATA	(1 << 1)
 
+/* DM should init this device prior to relocation */
+#define DM_FLAG_PRE_RELOC	(1 << 2)
+
 /**
  * struct udevice - An instance of a driver
  *
@@ -48,10 +51,13 @@ struct driver_info;
  * @priv: Private data for this device
  * @uclass: Pointer to uclass for this device
  * @uclass_priv: The uclass's private data for this device
+ * @parent_priv: The parent's private data for this device
  * @uclass_node: Used by uclass to link its devices
  * @child_head: List of children of this device
  * @sibling_node: Next device in list of all devices
  * @flags: Flags for this device DM_FLAG_...
+ * @req_seq: Requested sequence number for this device (-1 = any)
+ * @seq: Allocated sequence number for this device (-1 = none)
  */
 struct udevice {
 	struct driver *driver;
@@ -62,12 +68,18 @@ struct udevice {
 	void *priv;
 	struct uclass *uclass;
 	void *uclass_priv;
+	void *parent_priv;
 	struct list_head uclass_node;
 	struct list_head child_head;
 	struct list_head sibling_node;
 	uint32_t flags;
+	int req_seq;
+	int seq;
 };
 
+/* Maximum sequence number supported */
+#define DM_MAX_SEQ	999
+
 /* Returns the operations for a device */
 #define device_get_ops(dev)	(dev->driver->ops)
 
@@ -106,6 +118,10 @@ struct udevice_id {
  * @remove: Called to remove a device, i.e. de-activate it
  * @unbind: Called to unbind a device from its driver
  * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @child_pre_probe: Called before a child device is probed. The device has
+ * memory allocated but it has not yet been probed.
+ * @child_post_remove: Called after a child device is removed. The device
+ * has memory allocated but its device_remove() method has been called.
  * @priv_auto_alloc_size: If non-zero this is the size of the private data
  * to be allocated in the device's ->priv pointer. If zero, then the driver
  * is responsible for allocating any data required.
@@ -114,9 +130,13 @@ struct udevice_id {
  * This is typically only useful for device-tree-aware drivers (those with
  * an of_match), since drivers which use platdata will have the data
  * provided in the U_BOOT_DEVICE() instantiation.
- * ops: Driver-specific operations. This is typically a list of function
+ * @per_child_auto_alloc_size: Each device can hold private data owned by
+ * its parent. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Driver-specific operations. This is typically a list of function
  * pointers defined by the driver, to implement driver functions required by
  * the uclass.
+ * @flags: driver flags - see DM_FLAGS_...
  */
 struct driver {
 	char *name;
@@ -127,9 +147,13 @@ struct driver {
 	int (*remove)(struct udevice *dev);
 	int (*unbind)(struct udevice *dev);
 	int (*ofdata_to_platdata)(struct udevice *dev);
+	int (*child_pre_probe)(struct udevice *dev);
+	int (*child_post_remove)(struct udevice *dev);
 	int priv_auto_alloc_size;
 	int platdata_auto_alloc_size;
+	int per_child_auto_alloc_size;
 	const void *ops;	/* driver-specific operations */
+	uint32_t flags;
 };
 
 /* Declare a new U-Boot driver */
@@ -147,6 +171,20 @@ struct driver {
 void *dev_get_platdata(struct udevice *dev);
 
 /**
+ * dev_get_parentdata() - Get the parent data for a device
+ *
+ * The parent data is data stored in the device but owned by the parent.
+ * For example, a USB device may have parent data which contains information
+ * about how to talk to the device over USB.
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return parent data, or NULL if none
+ */
+void *dev_get_parentdata(struct udevice *dev);
+
+/**
  * dev_get_priv() - Get the private data for a device
  *
  * This checks that dev is not NULL, but no other checks for now
@@ -156,4 +194,84 @@ void *dev_get_platdata(struct udevice *dev);
  */
 void *dev_get_priv(struct udevice *dev);
 
+/**
+ * device_get_child() - Get the child of a device by index
+ *
+ * Returns the numbered child, 0 being the first. This does not use
+ * sequence numbers, only the natural order.
+ *
+ * @dev:	Parent device to check
+ * @index:	Child index
+ * @devp:	Returns pointer to device
+ */
+int device_get_child(struct udevice *parent, int index, struct udevice **devp);
+
+/**
+ * device_find_child_by_seq() - Find a child device based on a sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * @parent: Parent device
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq).
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
+			     bool find_req_seq, struct udevice **devp);
+
+/**
+ * device_get_child_by_seq() - Get a child device based on a sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_seq(struct udevice *parent, int seq,
+			    struct udevice **devp);
+
+/**
+ * device_find_child_by_of_offset() - Find a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
+				   struct udevice **devp);
+
+/**
+ * device_get_child_by_of_offset() - Get a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_of_offset(struct udevice *parent, int seq,
+				  struct udevice **devp);
+
 #endif
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 49d87e6176..87a3af59c2 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -42,7 +42,7 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
  * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false
  * bind all drivers.
  */
-int lists_bind_drivers(struct udevice *parent);
+int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only);
 
 /**
  * lists_bind_fdt() - bind a device tree node
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
index 0ef3353e74..2bc8b147ed 100644
--- a/include/dm/platdata.h
+++ b/include/dm/platdata.h
@@ -11,9 +11,15 @@
 #ifndef _DM_PLATDATA_H
 #define _DM_PLATDATA_H
 
+/**
+ * struct driver_info - Information required to instantiate a device
+ *
+ * @name:	Device name
+ * @platdata:	Driver-specific platform data
+ */
 struct driver_info {
-	const char	*name;
-	const void	*platdata;
+	const char *name;
+	const void *platdata;
 };
 
 #define U_BOOT_DEVICE(__name)						\
diff --git a/include/dm/root.h b/include/dm/root.h
index a4826a6e3c..c7f0c1d5ca 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -26,19 +26,66 @@ struct udevice *dm_root(void);
  *
  * This scans all available platdata and creates drivers for each
  *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
  * @return 0 if OK, -ve on error
  */
-int dm_scan_platdata(void);
+int dm_scan_platdata(bool pre_reloc_only);
 
 /**
  * dm_scan_fdt() - Scan the device tree and bind drivers
  *
- * This scans the device tree and creates a driver for each node
+ * This scans the device tree and creates a driver for each node. Only
+ * the top-level subnodes are examined.
  *
  * @blob: Pointer to device tree blob
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
  * @return 0 if OK, -ve on error
  */
-int dm_scan_fdt(const void *blob);
+int dm_scan_fdt(const void *blob, bool pre_reloc_only);
+
+/**
+ * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node
+ *
+ * This scans the subnodes of a device tree node and and creates a driver
+ * for each one.
+ *
+ * @parent: Parent device for the devices that will be created
+ * @blob: Pointer to device tree blob
+ * @offset: Offset of node to scan
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
+		     bool pre_reloc_only);
+
+/**
+ * dm_scan_other() - Scan for other devices
+ *
+ * Some devices may not be visible to Driver Model. This weak function can
+ * be provided by boards which wish to create their own devices
+ * programmaticaly. They should do this by calling device_bind() on each
+ * device.
+ *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ */
+int dm_scan_other(bool pre_reloc_only);
+
+/**
+ * dm_init_and_scan() - Initialise Driver Model structures and scan for devices
+ *
+ * This function initialises the roots of the driver tree and uclass trees,
+ * then scans and binds available devices from platform data and the FDT.
+ * This calls dm_init() to set up Driver Model structures.
+ *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_init_and_scan(bool pre_reloc_only);
 
 /**
  * dm_init() - Initialise Driver Model structures
@@ -50,4 +97,12 @@ int dm_scan_fdt(const void *blob);
  */
 int dm_init(void);
 
+/**
+ * dm_uninit - Uninitialise Driver Model structures
+ *
+ * All devices will be removed and unbound
+ * @return 0 if OK, -ve on error
+ */
+int dm_uninit(void);
+
 #endif
diff --git a/include/dm/test.h b/include/dm/test.h
index 409f1a3667..235d728bfb 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -82,6 +82,17 @@ struct dm_test_uclass_priv {
 	int total_add;
 };
 
+/**
+ * struct dm_test_parent_data - parent's information on each child
+ *
+ * @sum: Test value used to check parent data works correctly
+ * @flag: Used to track calling of parent operations
+ */
+struct dm_test_parent_data {
+	int sum;
+	int flag;
+};
+
 /*
  * Operation counts for the test driver, used to check that each method is
  * called correctly
@@ -100,6 +111,7 @@ extern struct dm_test_state global_test_state;
  * @fail_count: Number of tests that failed
  * @force_fail_alloc: Force all memory allocs to fail
  * @skip_post_probe: Skip uclass post-probe processing
+ * @removed: Used to keep track of a device that was removed
  */
 struct dm_test_state {
 	struct udevice *root;
@@ -107,6 +119,7 @@ struct dm_test_state {
 	int fail_count;
 	int force_fail_alloc;
 	int skip_post_probe;
+	struct udevice *removed;
 };
 
 /* Test flags for each test */
@@ -156,6 +169,15 @@ int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
 			uint32_t base, struct dm_test_priv *priv);
 
 /**
+ * dm_check_devices() - check the devices respond to operations correctly
+ *
+ * @dms: Overall test state
+ * @num_devices: Number of test devices to check
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_devices(struct dm_test_state *dms, int num_devices);
+
+/**
  * dm_test_main() - Run all the tests
  *
  * This runs all available driver model tests
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f0e691c18c..dd95fca428 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -17,9 +17,10 @@ enum uclass_id {
 	UCLASS_DEMO,
 	UCLASS_TEST,
 	UCLASS_TEST_FDT,
+	UCLASS_TEST_BUS,
 
 	/* U-Boot uclasses start here */
-	UCLASS_GPIO,
+	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
 
 	UCLASS_COUNT,
 	UCLASS_INVALID = -1,
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index 1434db3eb4..f718f37aff 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -82,4 +82,27 @@ struct uclass *uclass_find(enum uclass_id key);
  */
 int uclass_destroy(struct uclass *uc);
 
+/**
+ * uclass_find_device_by_seq() - Find uclass device based on ID and sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
+			      bool find_req_seq, struct udevice **devp);
+
 #endif
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index afd9923fb3..8d09ecff7b 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -98,7 +98,7 @@ int uclass_get(enum uclass_id key, struct uclass **ucp);
  *
  * The device is probed to activate it ready for use.
  *
- * id: ID to look up
+ * @id: ID to look up
  * @index: Device number within that uclass (0=first)
  * @devp: Returns pointer to device (there is only one per for each ID)
  * @return 0 if OK, -ve on error
@@ -106,6 +106,38 @@ int uclass_get(enum uclass_id key, struct uclass **ucp);
 int uclass_get_device(enum uclass_id id, int index, struct udevice **devp);
 
 /**
+ * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp);
+
+/**
+ * uclass_get_device_by_of_offset() - Get a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_offset(enum uclass_id id, int node,
+				   struct udevice **devp);
+
+/**
  * uclass_first_device() - Get the first device in a uclass
  *
  * @id: Uclass ID to look up
@@ -124,6 +156,21 @@ int uclass_first_device(enum uclass_id id, struct udevice **devp);
 int uclass_next_device(struct udevice **devp);
 
 /**
+ * uclass_resolve_seq() - Resolve a device's sequence number
+ *
+ * On entry dev->seq is -1, and dev->req_seq may be -1 (to allocate a
+ * sequence number automatically, or >= 0 to select a particular number.
+ * If the requested sequence number is in use, then this device will
+ * be allocated another one.
+ *
+ * Note that the device's seq value is not changed by this function.
+ *
+ * @dev: Device for which to allocate sequence number
+ * @return sequence number allocated, or -ve on error
+ */
+int uclass_resolve_seq(struct udevice *dev);
+
+/**
  * uclass_foreach_dev() - Helper function to iteration through devices
  *
  * This creates a for() loop which works through the available devices in
diff --git a/include/env_callback.h b/include/env_callback.h
index f90a7fa3b6..ab4e115fb0 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -60,7 +60,7 @@ void env_callback_init(ENTRY *var_entry);
  */
 #ifdef CONFIG_SPL_BUILD
 #define U_BOOT_ENV_CALLBACK(name, callback) \
-	static inline void _u_boot_env_noop_##name(void) \
+	static inline __maybe_unused void _u_boot_env_noop_##name(void) \
 	{ \
 		(void)callback; \
 	}
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7fdf..856e6cf766 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -345,6 +345,35 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name,
 int fdtdec_add_aliases_for_id(const void *blob, const char *name,
 			enum fdt_compat_id id, int *node_list, int maxcount);
 
+/**
+ * Get the alias sequence number of a node
+ *
+ * This works out whether a node is pointed to by an alias, and if so, the
+ * sequence number of that alias. Aliases are of the form <base><num> where
+ * <num> is the sequence number. For example spi2 would be sequence number
+ * 2.
+ *
+ * @param blob		Device tree blob (if NULL, then error is returned)
+ * @param base		Base name for alias (before the underscore)
+ * @param node		Node to look up
+ * @param seqp		This is set to the sequence number if one is found,
+ *			but otherwise the value is left alone
+ * @return 0 if a sequence was found, -ve if not
+ */
+int fdtdec_get_alias_seq(const void *blob, const char *base, int node,
+			 int *seqp);
+
+/**
+ * Get the offset of the given alias node
+ *
+ * This looks up an alias in /aliases then finds the offset of that node.
+ *
+ * @param blob		Device tree blob (if NULL, then error is returned)
+ * @param name		Alias name, e.g. "console"
+ * @return Node offset referred to by that alias, or -ve FDT_ERR_...
+ */
+int fdtdec_get_alias_node(const void *blob, const char *name);
+
 /*
  * Get the name for a compatible ID
  *
diff --git a/include/i8042.h b/include/i8042.h
index 963061920c..58c85ec5f0 100644
--- a/include/i8042.h
+++ b/include/i8042.h
@@ -72,8 +72,10 @@ void i8042_flush(void);
  */
 int i8042_disable(void);
 
+struct stdio_dev;
+
 int i8042_kbd_init(void);
-int i8042_tstc(void);
-int i8042_getc(void);
+int i8042_tstc(struct stdio_dev *dev);
+int i8042_getc(struct stdio_dev *dev);
 
 #endif /* _I8042_H_ */
diff --git a/include/ide.h b/include/ide.h
index 0424d045a1..c2a48e0b37 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -66,12 +66,16 @@ void ide_write_data(int dev, const ulong *sect_buf, int words);
 /*
  * I/O function overrides
  */
+unsigned char ide_inb(int dev, int port);
+void ide_outb(int dev, int port, unsigned char val);
 void ide_input_swap_data(int dev, ulong *sect_buf, int words);
 void ide_input_data(int dev, ulong *sect_buf, int words);
 void ide_output_data(int dev, const ulong *sect_buf, int words);
 void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
 void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
 
+void ide_led(uchar led, uchar status);
+
 /**
  * board_start_ide() - Start up the board IDE interfac
  *
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 3fdfb399b5..35e216e06e 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -57,4 +57,23 @@
 				  , __FILE__, __LINE__); }
 
 #define PAGE_SIZE	4096
+
+/**
+ * upper_32_bits - return MSB bits 32-63 of a number if little endian, or
+ * return MSB bits 0-31 of a number if big endian.
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * lower_32_bits - return LSB bits 0-31 of a number if little endian, or
+ * return LSB bits 32-63 of a number if big endian.
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((u32)(n))
+
 #endif
diff --git a/include/mmc.h b/include/mmc.h
index f46572e177..7f5f9bc8ca 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -327,10 +327,11 @@ struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
 int get_mmc_num(void);
-int board_mmc_getcd(struct mmc *mmc);
 int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_getcd(struct mmc *mmc);
+int board_mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
+int board_mmc_getwp(struct mmc *mmc);
 int mmc_set_dsr(struct mmc *mmc, u16 val);
 /* Function to change the size of boot partition and rpmb partitions */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
@@ -385,6 +386,7 @@ int mmc_legacy_init(int verbose);
 #endif
 
 int board_mmc_init(bd_t *bis);
+int cpu_mmc_init(bd_t *bis);
 
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
diff --git a/include/netdev.h b/include/netdev.h
index 63481eca22..e45dd7abec 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis);
 int skge_initialize(bd_t *bis);
 int smc91111_initialize(u8 dev_num, int base_addr);
 int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_emac_initialize(bd_t *bis);
 int sunxi_gmac_initialize(bd_t *bis);
-int sunxi_wemac_initialize(bd_t *bis);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
diff --git a/include/power/pmic.h b/include/power/pmic.h
index a62e6c90a5..afbc5aab7e 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -79,6 +79,7 @@ struct pmic {
 };
 
 int pmic_init(unsigned char bus);
+int power_init_board(void);
 int pmic_dialog_init(unsigned char bus);
 int check_reg(struct pmic *p, u32 reg);
 struct pmic *pmic_alloc(void);
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
index 67aa2f8c8d..f8f33b8b16 100644
--- a/include/power/tps65218.h
+++ b/include/power/tps65218.h
@@ -60,4 +60,5 @@ enum {
 int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
 		       uchar mask);
 int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+int power_tps65218_init(unsigned char bus);
 #endif	/* __POWER_TPS65218_H__ */
diff --git a/include/search.h b/include/search.h
index ae3efc43ca..9701efb2df 100644
--- a/include/search.h
+++ b/include/search.h
@@ -102,7 +102,8 @@ extern ssize_t hexport_r(struct hsearch_data *__htab,
  */
 extern int himport_r(struct hsearch_data *__htab,
 		     const char *__env, size_t __size, const char __sep,
-		     int __flag, int nvars, char * const vars[]);
+		     int __flag, int __crlf_is_lf, int nvars,
+		     char * const vars[]);
 
 /* Walk the whole table calling the callback on each element */
 extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *));
diff --git a/include/status_led.h b/include/status_led.h
index 0eb91b8695..b8aaaf78fc 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -272,19 +272,21 @@ extern void __led_set (led_id_t mask, int state);
 # include <asm/status_led.h>
 #endif
 
+#endif	/* CONFIG_STATUS_LED	*/
+
 /*
  * Coloured LEDs API
  */
 #ifndef	__ASSEMBLY__
-extern void	coloured_LED_init (void);
-extern void	red_led_on(void);
-extern void	red_led_off(void);
-extern void	green_led_on(void);
-extern void	green_led_off(void);
-extern void	yellow_led_on(void);
-extern void	yellow_led_off(void);
-extern void	blue_led_on(void);
-extern void	blue_led_off(void);
+void coloured_LED_init(void);
+void red_led_on(void);
+void red_led_off(void);
+void green_led_on(void);
+void green_led_off(void);
+void yellow_led_on(void);
+void yellow_led_off(void);
+void blue_led_on(void);
+void blue_led_off(void);
 #else
 	.extern LED_init
 	.extern red_led_on
@@ -297,6 +299,4 @@ extern void	blue_led_off(void);
 	.extern blue_led_off
 #endif
 
-#endif	/* CONFIG_STATUS_LED	*/
-
 #endif	/* _STATUS_LED_H_	*/
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index e6dc12ac39..a7d0825c7e 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -27,18 +27,21 @@ struct stdio_dev {
 
 /* GENERAL functions */
 
-	int (*start) (void);		/* To start the device			*/
-	int (*stop) (void);		/* To stop the device			*/
+	int (*start)(struct stdio_dev *dev);	/* To start the device */
+	int (*stop)(struct stdio_dev *dev);	/* To stop the device */
 
 /* OUTPUT functions */
 
-	void (*putc) (const char c);	/* To put a char			*/
-	void (*puts) (const char *s);	/* To put a string (accelerator)	*/
+	/* To put a char */
+	void (*putc)(struct stdio_dev *dev, const char c);
+	/* To put a string (accelerator) */
+	void (*puts)(struct stdio_dev *dev, const char *s);
 
 /* INPUT functions */
 
-	int (*tstc) (void);		/* To test if a char is ready...	*/
-	int (*getc) (void);		/* To get that char			*/
+	/* To test if a char is ready... */
+	int (*tstc)(struct stdio_dev *dev);
+	int (*getc)(struct stdio_dev *dev);	/* To get that char */
 
 /* Other functions */
 
@@ -74,10 +77,12 @@ extern char *stdio_names[MAX_FILES];
  * PROTOTYPES
  */
 int	stdio_register (struct stdio_dev * dev);
+int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp);
 int	stdio_init (void);
 void	stdio_print_current_devices(void);
 #ifdef CONFIG_SYS_STDIO_DEREGISTER
 int	stdio_deregister(const char *devname);
+int stdio_deregister_dev(struct stdio_dev *dev);
 #endif
 struct list_head* stdio_get_list(void);
 struct stdio_dev* stdio_get_by_name(const char* name);
diff --git a/include/video.h b/include/video.h
index 0ff857bc9f..673aa2ec56 100644
--- a/include/video.h
+++ b/include/video.h
@@ -11,9 +11,11 @@
 
 /* Video functions */
 
-int	video_init	(void *videobase);
-void	video_putc	(const char c);
-void	video_puts	(const char *s);
+struct stdio_dev;
+
+int	video_init(void *videobase);
+void	video_putc(struct stdio_dev *dev, const char c);
+void	video_puts(struct stdio_dev *dev, const char *s);
 
 /**
  * Display a BMP format bitmap on the screen
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 6ea7b03ad4..129bc3e2af 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -28,6 +28,9 @@ int main(void)
 	DEFINE(GD_SIZE, sizeof(struct global_data));
 
 	DEFINE(GD_BD, offsetof(struct global_data, bd));
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
+#endif
 
 #if defined(CONFIG_ARM)
 
diff --git a/lib/div64.c b/lib/div64.c
index e688a91200..795ef0e1e4 100644
--- a/lib/div64.c
+++ b/lib/div64.c
@@ -16,6 +16,7 @@
  * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S.
  */
 
+#include <div64.h>
 #include <linux/types.h>
 
 uint32_t __div64_32(uint64_t *n, uint32_t base)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index aaa6620cc3..eb5aa20526 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -5,9 +5,11 @@
 
 #ifndef USE_HOSTCC
 #include <common.h>
+#include <errno.h>
 #include <serial.h>
 #include <libfdt.h>
 #include <fdtdec.h>
+#include <linux/ctype.h>
 
 #include <asm/gpio.h>
 
@@ -319,6 +321,65 @@ int fdtdec_add_aliases_for_id(const void *blob, const char *name,
 	return num_found;
 }
 
+int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
+			 int *seqp)
+{
+	int base_len = strlen(base);
+	const char *find_name;
+	int find_namelen;
+	int prop_offset;
+	int aliases;
+
+	find_name = fdt_get_name(blob, offset, &find_namelen);
+	debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
+
+	aliases = fdt_path_offset(blob, "/aliases");
+	for (prop_offset = fdt_first_property_offset(blob, aliases);
+	     prop_offset > 0;
+	     prop_offset = fdt_next_property_offset(blob, prop_offset)) {
+		const char *prop;
+		const char *name;
+		const char *slash;
+		const char *p;
+		int len;
+
+		prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
+		debug("   - %s, %s\n", name, prop);
+		if (len < find_namelen || *prop != '/' || prop[len - 1] ||
+		    strncmp(name, base, base_len))
+			continue;
+
+		slash = strrchr(prop, '/');
+		if (strcmp(slash + 1, find_name))
+			continue;
+		for (p = name; *p; p++) {
+			if (isdigit(*p)) {
+				*seqp = simple_strtoul(p, NULL, 10);
+				debug("Found seq %d\n", *seqp);
+				return 0;
+			}
+		}
+	}
+
+	debug("Not found\n");
+	return -ENOENT;
+}
+
+int fdtdec_get_alias_node(const void *blob, const char *name)
+{
+	const char *prop;
+	int alias_node;
+	int len;
+
+	if (!blob)
+		return -FDT_ERR_NOTFOUND;
+	alias_node = fdt_path_offset(blob, "/aliases");
+	prop = fdt_getprop(blob, alias_node, name, &len);
+	if (!prop)
+		return -FDT_ERR_NOTFOUND;
+	return fdt_path_offset(blob, prop);
+}
+
 int fdtdec_check_fdt(void)
 {
 	/*
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 4356b234ec..18ed5901ec 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -776,7 +776,7 @@ static int drop_var_from_set(const char *name, int nvars, char * vars[])
 
 int himport_r(struct hsearch_data *htab,
 		const char *env, size_t size, const char sep, int flag,
-		int nvars, char * const vars[])
+		int crlf_is_lf, int nvars, char * const vars[])
 {
 	char *data, *sp, *dp, *name, *value;
 	char *localvars[nvars];
@@ -841,6 +841,21 @@ int himport_r(struct hsearch_data *htab,
 		}
 	}
 
+	if(!size)
+		return 1;		/* everything OK */
+	if(crlf_is_lf) {
+		/* Remove Carriage Returns in front of Line Feeds */
+		unsigned ignored_crs = 0;
+		for(;dp < data + size && *dp; ++dp) {
+			if(*dp == '\r' &&
+			   dp < data + size - 1 && *(dp+1) == '\n')
+				++ignored_crs;
+			else
+				*(dp-ignored_crs) = *dp;
+		}
+		size -= ignored_crs;
+		dp = data;
+	}
 	/* Parse environment; allow for '\0' and 'sep' as separators */
 	do {
 		ENTRY e, *rv;
diff --git a/lib/lmb.c b/lib/lmb.c
index 081e4181b4..49a3c9e01e 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -332,14 +332,12 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
 	return 0;
 }
 
-void __board_lmb_reserve(struct lmb *lmb)
+__weak void board_lmb_reserve(struct lmb *lmb)
 {
 	/* please define platform specific board_lmb_reserve() */
 }
-void board_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__board_lmb_reserve")));
 
-void __arch_lmb_reserve(struct lmb *lmb)
+__weak void arch_lmb_reserve(struct lmb *lmb)
 {
 	/* please define platform specific arch_lmb_reserve() */
 }
-void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve")));
diff --git a/lib/sha1.c b/lib/sha1.c
index 0a5f68864c..05b17a259a 100644
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -389,8 +389,6 @@ void sha1_hmac(const unsigned char *key, int keylen,
 	memset (&ctx, 0, sizeof (sha1_context));
 }
 
-static const char _sha1_src[] = "_sha1_src";
-
 #ifdef SELF_TEST
 /*
  * FIPS-180-1 test vectors
diff --git a/lib/time.c b/lib/time.c
index 73c3b6ad7f..c7b026498b 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -15,12 +15,13 @@
 #endif
 
 #ifndef CONFIG_WD_PERIOD
-# define CONFIG_WD_PERIOD	(10 * 1000 * 1000)	/* 10 seconds default*/
+# define CONFIG_WD_PERIOD	(10 * 1000 * 1000)	/* 10 seconds default */
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SYS_TIMER_RATE
+/* Returns tick rate in ticks per second */
 ulong notrace get_tbclk(void)
 {
 	return CONFIG_SYS_TIMER_RATE;
@@ -51,9 +52,10 @@ unsigned long long __weak notrace get_ticks(void)
 	return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
 }
 
-static unsigned long long notrace tick_to_time(uint64_t tick)
+/* Returns time in milliseconds */
+static unsigned long long notrace tick_to_time(unsigned long long tick)
 {
-	unsigned int div = get_tbclk();
+	ulong div = get_tbclk();
 
 	tick *= CONFIG_SYS_HZ;
 	do_div(tick, div);
@@ -65,6 +67,7 @@ int __weak timer_init(void)
 	return 0;
 }
 
+/* Returns time in milliseconds */
 ulong __weak get_timer(ulong base)
 {
 	return tick_to_time(get_ticks()) - base;
@@ -74,9 +77,10 @@ unsigned long __weak notrace timer_get_us(void)
 {
 	return tick_to_time(get_ticks() * 1000);
 }
+
 static unsigned long long usec_to_tick(unsigned long usec)
 {
-	uint64_t tick = usec;
+	unsigned long long tick = usec;
 	tick *= get_tbclk();
 	do_div(tick, 1000000);
 	return tick;
@@ -85,12 +89,10 @@ static unsigned long long usec_to_tick(unsigned long usec)
 void __weak __udelay(unsigned long usec)
 {
 	unsigned long long tmp;
-	ulong tmo;
 
-	tmo = usec_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
+	tmp = get_ticks() + usec_to_tick(usec);	/* get current timestamp */
 
-	while (get_ticks() < tmp)	/* loop till event */
+	while (get_ticks() < tmp+1)	/* loop till event */
 		 /*NOP*/;
 }
 
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 60874dae3e..7ec758e40f 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -28,17 +28,6 @@
 /* some reluctance to put this into a new limits.h, so it is here */
 #define INT_MAX		((int)(~0U>>1))
 
-static const char hex_asc[] = "0123456789abcdef";
-#define hex_asc_lo(x)   hex_asc[((x) & 0x0f)]
-#define hex_asc_hi(x)   hex_asc[((x) & 0xf0) >> 4]
-
-static inline char *pack_hex_byte(char *buf, u8 byte)
-{
-	*buf++ = hex_asc_hi(byte);
-	*buf++ = hex_asc_lo(byte);
-	return buf;
-}
-
 unsigned long simple_strtoul(const char *cp, char **endp,
 				unsigned int base)
 {
@@ -434,6 +423,17 @@ static char *string(char *buf, char *end, char *s, int field_width,
 }
 
 #ifdef CONFIG_CMD_NET
+static const char hex_asc[] = "0123456789abcdef";
+#define hex_asc_lo(x)	hex_asc[((x) & 0x0f)]
+#define hex_asc_hi(x)	hex_asc[((x) & 0xf0) >> 4]
+
+static inline char *pack_hex_byte(char *buf, u8 byte)
+{
+	*buf++ = hex_asc_hi(byte);
+	*buf++ = hex_asc_lo(byte);
+	return buf;
+}
+
 static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width,
 				int precision, int flags)
 {
diff --git a/net/bootp.c b/net/bootp.c
index 189a003835..fdb97cb562 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -605,7 +605,7 @@ BootpRequest(void)
 	int extlen, pktlen, iplen;
 	int eth_hdr_size;
 #ifdef CONFIG_BOOTP_RANDOM_DELAY
-	ulong i, rand_ms;
+	ulong rand_ms;
 #endif
 
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTP_START, "bootp_start");
@@ -623,8 +623,7 @@ BootpRequest(void)
 		rand_ms = rand() >> 19;
 
 	printf("Random delay: %ld ms...\n", rand_ms);
-	for (i = 0; i < rand_ms; i++)
-		udelay(1000); /*Wait 1ms*/
+	mdelay(rand_ms);
 
 #endif	/* CONFIG_BOOTP_RANDOM_DELAY */
 
diff --git a/net/eth.c b/net/eth.c
index 99386e3e63..76ffa05608 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -10,6 +10,7 @@
 #include <net.h>
 #include <miiphy.h>
 #include <phy.h>
+#include <asm/errno.h>
 
 void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
 {
@@ -152,6 +153,11 @@ static void eth_current_changed(void)
 		setenv("ethact", NULL);
 }
 
+int eth_address_set(unsigned char *addr)
+{
+	return memcmp(addr, "\0\0\0\0\0\0", 6);
+}
+
 int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 		   int eth_number)
 {
@@ -160,8 +166,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 
 	eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr);
 
-	if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
-		if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) &&
+	if (eth_address_set(env_enetaddr)) {
+		if (eth_address_set(dev->enetaddr) &&
 				memcmp(dev->enetaddr, env_enetaddr, 6)) {
 			printf("\nWarning: %s MAC addresses don't match:\n",
 				dev->name);
@@ -177,14 +183,22 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 					     dev->enetaddr);
 		printf("\nWarning: %s using MAC address from net device\n",
 			dev->name);
+	} else if (!(eth_address_set(dev->enetaddr))) {
+		printf("\nError: %s address not set.\n",
+		       dev->name);
+		return -EINVAL;
 	}
 
-	if (dev->write_hwaddr &&
-			!eth_mac_skip(eth_number)) {
-		if (!is_valid_ether_addr(dev->enetaddr))
-			return -1;
+	if (dev->write_hwaddr && !eth_mac_skip(eth_number)) {
+		if (!is_valid_ether_addr(dev->enetaddr)) {
+			printf("\nError: %s address %pM illegal value\n",
+				 dev->name, dev->enetaddr);
+			return -EINVAL;
+		}
 
 		ret = dev->write_hwaddr(dev);
+		if (ret)
+			printf("\nWarning: %s failed to set MAC address\n", dev->name);
 	}
 
 	return ret;
@@ -303,8 +317,7 @@ int eth_initialize(bd_t *bis)
 				puts("\nWarning: eth device name has a space!"
 					"\n");
 
-			if (eth_write_hwaddr(dev, "eth", dev->index))
-				puts("\nWarning: failed to set MAC address\n");
+			eth_write_hwaddr(dev, "eth", dev->index);
 
 			dev = dev->next;
 			num_devices++;
diff --git a/scripts/mailmapper b/scripts/mailmapper
new file mode 100755
index 0000000000..dd1ddf6a71
--- /dev/null
+++ b/scripts/mailmapper
@@ -0,0 +1,160 @@
+#!/usr/bin/env python
+#
+# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+'''
+A tool to create/update the mailmap file
+
+The command 'git shortlog' summarizes git log output in a format suitable
+for inclusion in release announcements. Each commit will be grouped by
+author and title.
+
+One problem is that the authors' name and/or email address is sometimes
+spelled differently. The .mailmap feature can be used to coalesce together
+commits by the same persion.
+(See 'man git-shortlog' for furthur information of this feature.)
+
+This tool helps to create/update the mailmap file.
+
+It runs 'git shortlog' internally and searches differently spelled author
+names which share the same email address. The author name with the most
+commits is asuumed to be a canonical real name. If the number of commits
+from the cananonical name is equal to or greater than 'MIN_COMMITS',
+the entry for the cananical name will be output. ('MIN_COMMITS' is used
+here because we do not want to create a fat mailmap by adding every author
+with only a few commits.)
+
+If there exists a mailmap file specified by the mailmap.file configuration
+options or '.mailmap' at the toplevel of the repository, it is used as
+a base file. (The mailmap.file configuration takes precedence over the
+'.mailmap' file if both exist.)
+
+The base file and the newly added entries are merged together and sorted
+alphabetically (but the comment block is kept untouched), and then printed
+to standard output.
+
+Usage
+-----
+
+  scripts/mailmapper
+
+prints the mailmapping to standard output.
+
+  scripts/mailmapper > tmp; mv tmp .mailmap
+
+will be useful for updating '.mailmap' file.
+'''
+
+import sys
+import os
+import subprocess
+
+# The entries only for the canonical names with MIN_COMMITS or more commits.
+# This limitation is used so as not to create a too big mailmap file.
+MIN_COMMITS = 50
+
+try:
+    toplevel = subprocess.check_output(['git', 'rev-parse', '--show-toplevel'])
+except subprocess.CalledProcessError:
+    print >> sys.stderr, 'Please run in a git repository.'
+    sys.exit(1)
+
+# strip '\n'
+toplevel = toplevel.rstrip()
+
+# Change the current working directory to the toplevel of the respository
+# for our easier life.
+os.chdir(toplevel)
+
+# First, create 'auther name' vs 'number of commits' database.
+# We assume the name with the most commits as the canonical real name.
+shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n'])
+
+commits_per_name = {}
+
+for line in shortlog.splitlines():
+    try:
+        commits, name = line.split(None, 1)
+    except ValueError:
+        # ignore lines with an empty author name
+        pass
+    commits_per_name[name] = int(commits)
+
+# Next, coalesce the auther names with the same email address
+shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n', '-e'])
+
+mail_vs_name = {}
+output = {}
+
+for line in shortlog.splitlines():
+    # tmp, mail = line.rsplit(None, 1) is not safe
+    # because weird email addresses might include whitespaces
+    tmp, mail = line.split('<')
+    mail = '<' + mail.rstrip()
+    try:
+        _, name = tmp.rstrip().split(None, 1)
+    except ValueError:
+        # author name is empty
+        name = ''
+    if mail in mail_vs_name:
+        # another name for the same email address
+        prev_name = mail_vs_name[mail]
+        # Take the name with more commits
+        major_name = sorted([prev_name, name],
+                            key=lambda x: commits_per_name[x] if x else 0)[1]
+        mail_vs_name[mail] = major_name
+        if commits_per_name[major_name] > MIN_COMMITS:
+            output[mail] = major_name
+    else:
+        mail_vs_name[mail] = name
+
+# [1] If there exists a mailmap file at the location pointed to
+#     by the mailmap.file configuration option, update it.
+# [2] If the file .mailmap exists at the toplevel of the repository, update it.
+# [3] Otherwise, create a new mailmap file.
+mailmap_files = []
+
+try:
+    config_mailmap = subprocess.check_output(['git', 'config', 'mailmap.file'])
+except subprocess.CalledProcessError:
+    config_mailmap = ''
+
+config_mailmap = config_mailmap.rstrip()
+if config_mailmap:
+    mailmap_files.append(config_mailmap)
+
+mailmap_files.append('.mailmap')
+
+infile = None
+
+for map_file in mailmap_files:
+    try:
+        infile = open(map_file)
+    except:
+        # Failed to open. Try next.
+        continue
+    break
+
+comment_block = []
+output_lines = []
+
+if infile:
+    for line in infile:
+        if line[0] == '#' or line[0] == '\n':
+            comment_block.append(line)
+        else:
+            output_lines.append(line)
+            break
+    for line in infile:
+        output_lines.append(line)
+    infile.close()
+
+for mail, name in output.items():
+    output_lines.append(name + ' ' + mail + '\n')
+
+output_lines.sort()
+
+sys.stdout.write(''.join(comment_block + output_lines))
diff --git a/test/dm/Makefile b/test/dm/Makefile
index c0f21351d7..5c2415e3d2 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_CMD_DM) += cmd_dm.o
+obj-$(CONFIG_DM_TEST) += bus.o
 obj-$(CONFIG_DM_TEST) += test-driver.o
 obj-$(CONFIG_DM_TEST) += test-fdt.o
 obj-$(CONFIG_DM_TEST) += test-main.o
diff --git a/test/dm/bus.c b/test/dm/bus.c
new file mode 100644
index 0000000000..873d64e42a
--- /dev/null
+++ b/test/dm/bus.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	FLAG_CHILD_PROBED	= 10,
+	FLAG_CHILD_REMOVED	= -7,
+};
+
+static struct dm_test_state *test_state;
+
+static int testbus_drv_probe(struct udevice *dev)
+{
+	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+static int testbus_child_pre_probe(struct udevice *dev)
+{
+	struct dm_test_parent_data *parent_data = dev_get_parentdata(dev);
+
+	parent_data->flag += FLAG_CHILD_PROBED;
+
+	return 0;
+}
+
+static int testbus_child_post_remove(struct udevice *dev)
+{
+	struct dm_test_parent_data *parent_data = dev_get_parentdata(dev);
+	struct dm_test_state *dms = test_state;
+
+	parent_data->flag += FLAG_CHILD_REMOVED;
+	if (dms)
+		dms->removed = dev;
+
+	return 0;
+}
+
+static const struct udevice_id testbus_ids[] = {
+	{
+		.compatible = "denx,u-boot-test-bus",
+		.data = DM_TEST_TYPE_FIRST },
+	{ }
+};
+
+U_BOOT_DRIVER(testbus_drv) = {
+	.name	= "testbus_drv",
+	.of_match	= testbus_ids,
+	.id	= UCLASS_TEST_BUS,
+	.probe	= testbus_drv_probe,
+	.priv_auto_alloc_size = sizeof(struct dm_test_priv),
+	.platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+	.per_child_auto_alloc_size = sizeof(struct dm_test_parent_data),
+	.child_pre_probe = testbus_child_pre_probe,
+	.child_post_remove = testbus_child_post_remove,
+};
+
+UCLASS_DRIVER(testbus) = {
+	.name		= "testbus",
+	.id		= UCLASS_TEST_BUS,
+};
+
+/* Test that we can probe for children */
+static int dm_test_bus_children(struct dm_test_state *dms)
+{
+	int num_devices = 4;
+	struct udevice *bus;
+	struct uclass *uc;
+
+	ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+	ut_asserteq(num_devices, list_count_items(&uc->dev_head));
+
+	/* Probe the bus, which should yield 3 more devices */
+	ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+	num_devices += 3;
+
+	ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+	ut_asserteq(num_devices, list_count_items(&uc->dev_head));
+
+	ut_assert(!dm_check_devices(dms, num_devices));
+
+	return 0;
+}
+DM_TEST(dm_test_bus_children, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test our functions for accessing children */
+static int dm_test_bus_children_funcs(struct dm_test_state *dms)
+{
+	const void *blob = gd->fdt_blob;
+	struct udevice *bus, *dev;
+	int node;
+
+	ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+
+	/* device_get_child() */
+	ut_assertok(device_get_child(bus, 0, &dev));
+	ut_asserteq(-ENODEV, device_get_child(bus, 4, &dev));
+	ut_assertok(device_get_child_by_seq(bus, 5, &dev));
+	ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+	ut_asserteq_str("c-test@5", dev->name);
+
+	/* Device with sequence number 0 should be accessible */
+	ut_asserteq(-ENODEV, device_find_child_by_seq(bus, -1, true, &dev));
+	ut_assertok(device_find_child_by_seq(bus, 0, true, &dev));
+	ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+	ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 0, false, &dev));
+	ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+	ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+	/* There is no device with sequence number 2 */
+	ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, false, &dev));
+	ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, true, &dev));
+	ut_asserteq(-ENODEV, device_get_child_by_seq(bus, 2, &dev));
+
+	/* Looking for something that is not a child */
+	node = fdt_path_offset(blob, "/junk");
+	ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev));
+	node = fdt_path_offset(blob, "/d-test");
+	ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev));
+
+	/* Find a valid child */
+	node = fdt_path_offset(blob, "/some-bus/c-test@1");
+	ut_assertok(device_find_child_by_of_offset(bus, node, &dev));
+	ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+	ut_assertok(device_get_child_by_of_offset(bus, node, &dev));
+	ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+	return 0;
+}
+DM_TEST(dm_test_bus_children_funcs, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that the bus can store data about each child */
+static int dm_test_bus_parent_data(struct dm_test_state *dms)
+{
+	struct dm_test_parent_data *parent_data;
+	struct udevice *bus, *dev;
+	struct uclass *uc;
+	int value;
+
+	ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+
+	/* Check that parent data is allocated */
+	ut_assertok(device_find_child_by_seq(bus, 0, true, &dev));
+	ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+	ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+	parent_data = dev_get_parentdata(dev);
+	ut_assert(NULL != parent_data);
+
+	/* Check that it starts at 0 and goes away when device is removed */
+	parent_data->sum += 5;
+	ut_asserteq(5, parent_data->sum);
+	device_remove(dev);
+	ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+
+	/* Check that we can do this twice */
+	ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+	parent_data = dev_get_parentdata(dev);
+	ut_assert(NULL != parent_data);
+	parent_data->sum += 5;
+	ut_asserteq(5, parent_data->sum);
+
+	/* Add parent data to all children */
+	ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+	value = 5;
+	uclass_foreach_dev(dev, uc) {
+		/* Ignore these if they are not on this bus */
+		if (dev->parent != bus) {
+			ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+			continue;
+		}
+		ut_assertok(device_probe(dev));
+		parent_data = dev_get_parentdata(dev);
+
+		parent_data->sum = value;
+		value += 5;
+	}
+
+	/* Check it is still there */
+	value = 5;
+	uclass_foreach_dev(dev, uc) {
+		/* Ignore these if they are not on this bus */
+		if (dev->parent != bus)
+			continue;
+		parent_data = dev_get_parentdata(dev);
+
+		ut_asserteq(value, parent_data->sum);
+		value += 5;
+	}
+
+	return 0;
+}
+
+DM_TEST(dm_test_bus_parent_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that the bus ops are called when a child is probed/removed */
+static int dm_test_bus_parent_ops(struct dm_test_state *dms)
+{
+	struct dm_test_parent_data *parent_data;
+	struct udevice *bus, *dev;
+	struct uclass *uc;
+
+	test_state = dms;
+	ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+	ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+
+	uclass_foreach_dev(dev, uc) {
+		/* Ignore these if they are not on this bus */
+		if (dev->parent != bus)
+			continue;
+		ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+
+		ut_assertok(device_probe(dev));
+		parent_data = dev_get_parentdata(dev);
+		ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag);
+	}
+
+	uclass_foreach_dev(dev, uc) {
+		/* Ignore these if they are not on this bus */
+		if (dev->parent != bus)
+			continue;
+		parent_data = dev_get_parentdata(dev);
+		ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag);
+		ut_assertok(device_remove(dev));
+		ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+		ut_asserteq_ptr(dms->removed, dev);
+	}
+	test_state = NULL;
+
+	return 0;
+}
+DM_TEST(dm_test_bus_parent_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c
index 96f10f3b1d..26980d209f 100644
--- a/test/dm/cmd_dm.c
+++ b/test/dm/cmd_dm.c
@@ -16,6 +16,24 @@
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
 
+/**
+ * dm_display_line() - Display information about a single device
+ *
+ * Displays a single line of information with an option prefix
+ *
+ * @dev:	Device to display
+ * @buf:	Prefix to display at the start of the line
+ */
+static void dm_display_line(struct udevice *dev, char *buf)
+{
+	printf("%s- %c %s @ %08lx", buf,
+	       dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
+	       dev->name, (ulong)map_to_sysmem(dev));
+	if (dev->req_seq != -1)
+		printf(", %d", dev->req_seq);
+	puts("\n");
+}
+
 static int display_succ(struct udevice *in, char *buf)
 {
 	int len;
@@ -23,10 +41,7 @@ static int display_succ(struct udevice *in, char *buf)
 	char local[16];
 	struct udevice *pos, *n, *prev = NULL;
 
-	printf("%s- %c %s @ %08lx", buf,
-	       in->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
-	       in->name, (ulong)map_to_sysmem(in));
-	puts("\n");
+	dm_display_line(in, buf);
 
 	if (list_empty(&in->child_head))
 		return 0;
@@ -81,12 +96,10 @@ static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc,
 			continue;
 
 		printf("uclass %d: %s\n", id, uc->uc_drv->name);
-		for (ret = uclass_first_device(id, &dev);
-		     dev;
-		     ret = uclass_next_device(&dev)) {
-			printf("  %c %s @ %08lx:\n",
-			       dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
-			       dev->name, (ulong)map_to_sysmem(dev));
+		if (list_empty(&uc->dev_head))
+			continue;
+		list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+			dm_display_line(dev, "");
 		}
 		puts("\n");
 	}
@@ -135,7 +148,7 @@ static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	dm,	2,	1,	do_dm,
 	"Driver model low level access",
-	"tree         Dump driver model tree\n"
+	"tree         Dump driver model tree ('*' = activated)\n"
 	"dm uclass        Dump list of instances for each uclass"
 	TEST_HELP
 );
diff --git a/test/dm/core.c b/test/dm/core.c
index be3646b968..b0cfb42c85 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -25,6 +25,7 @@ enum {
 	TEST_INTVAL2		= 3,
 	TEST_INTVAL3		= 6,
 	TEST_INTVAL_MANUAL	= 101112,
+	TEST_INTVAL_PRE_RELOC	= 7,
 };
 
 static const struct dm_test_pdata test_pdata[] = {
@@ -37,6 +38,10 @@ static const struct dm_test_pdata test_pdata_manual = {
 	.ping_add		= TEST_INTVAL_MANUAL,
 };
 
+static const struct dm_test_pdata test_pdata_pre_reloc = {
+	.ping_add		= TEST_INTVAL_PRE_RELOC,
+};
+
 U_BOOT_DEVICE(dm_test_info1) = {
 	.name = "test_drv",
 	.platdata = &test_pdata[0],
@@ -57,6 +62,11 @@ static struct driver_info driver_info_manual = {
 	.platdata = &test_pdata_manual,
 };
 
+static struct driver_info driver_info_pre_reloc = {
+	.name = "test_pre_reloc_drv",
+	.platdata = &test_pdata_manual,
+};
+
 /* Test that binding with platdata occurs correctly */
 static int dm_test_autobind(struct dm_test_state *dms)
 {
@@ -71,7 +81,7 @@ static int dm_test_autobind(struct dm_test_state *dms)
 	ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
 	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
 
-	ut_assertok(dm_scan_platdata());
+	ut_assertok(dm_scan_platdata(false));
 
 	/* We should have our test class now at least, plus more children */
 	ut_assert(1 < list_count_items(&gd->uclass_root));
@@ -106,7 +116,7 @@ static int dm_test_autoprobe(struct dm_test_state *dms)
 	ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
 
 	/* The root device should not be activated until needed */
-	ut_assert(!(dms->root->flags & DM_FLAG_ACTIVATED));
+	ut_assert(dms->root->flags & DM_FLAG_ACTIVATED);
 
 	/*
 	 * We should be able to find the three test devices, and they should
@@ -181,7 +191,7 @@ static int dm_test_lifecycle(struct dm_test_state *dms)
 
 	memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
 
-	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
 					&dev));
 	ut_assert(dev);
 	ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND]
@@ -232,15 +242,15 @@ static int dm_test_ordering(struct dm_test_state *dms)
 	struct udevice *dev, *dev_penultimate, *dev_last, *test_dev;
 	int pingret;
 
-	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
 					&dev));
 	ut_assert(dev);
 
 	/* Bind two new devices (numbers 4 and 5) */
-	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
 					&dev_penultimate));
 	ut_assert(dev_penultimate);
-	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
 					&dev_last));
 	ut_assert(dev_last);
 
@@ -255,7 +265,8 @@ static int dm_test_ordering(struct dm_test_state *dms)
 	ut_assert(dev_last == test_dev);
 
 	/* Add back the original device 3, now in position 5 */
-	ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, &dev));
+	ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
+					&dev));
 	ut_assert(dev);
 
 	/* Try ping */
@@ -375,8 +386,8 @@ static int dm_test_leak(struct dm_test_state *dms)
 		if (!start.uordblks)
 			puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
 
-		ut_assertok(dm_scan_platdata());
-		ut_assertok(dm_scan_fdt(gd->fdt_blob));
+		ut_assertok(dm_scan_platdata(false));
+		ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
 
 		/* Scanning the uclass is enough to probe all the devices */
 		for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) {
@@ -444,8 +455,8 @@ static int create_children(struct dm_test_state *dms, struct udevice *parent,
 	for (i = 0; i < count; i++) {
 		struct dm_test_pdata *pdata;
 
-		ut_assertok(device_bind_by_name(parent, &driver_info_manual,
-						&dev));
+		ut_assertok(device_bind_by_name(parent, false,
+						&driver_info_manual, &dev));
 		pdata = calloc(1, sizeof(*pdata));
 		pdata->ping_add = key + i;
 		dev->platdata = pdata;
@@ -542,3 +553,34 @@ static int dm_test_children(struct dm_test_state *dms)
 	return 0;
 }
 DM_TEST(dm_test_children, 0);
+
+/* Test that pre-relocation devices work as expected */
+static int dm_test_pre_reloc(struct dm_test_state *dms)
+{
+	struct udevice *dev;
+
+	/* The normal driver should refuse to bind before relocation */
+	ut_asserteq(-EPERM, device_bind_by_name(dms->root, true,
+						&driver_info_manual, &dev));
+
+	/* But this one is marked pre-reloc */
+	ut_assertok(device_bind_by_name(dms->root, true,
+					&driver_info_pre_reloc, &dev));
+
+	return 0;
+}
+DM_TEST(dm_test_pre_reloc, 0);
+
+static int dm_test_uclass_before_ready(struct dm_test_state *dms)
+{
+	struct uclass *uc;
+
+	ut_assertok(uclass_get(UCLASS_TEST, &uc));
+
+	memset(gd, '\0', sizeof(*gd));
+	ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST));
+
+	return 0;
+}
+
+DM_TEST(dm_test_uclass_before_ready, 0);
diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c
index 0f1a37b36e..bc6a6e721d 100644
--- a/test/dm/test-driver.c
+++ b/test/dm/test-driver.c
@@ -144,3 +144,14 @@ U_BOOT_DRIVER(test_manual_drv) = {
 	.remove	= test_manual_remove,
 	.unbind	= test_manual_unbind,
 };
+
+U_BOOT_DRIVER(test_pre_reloc_drv) = {
+	.name	= "test_pre_reloc_drv",
+	.id	= UCLASS_TEST,
+	.ops	= &test_manual_ops,
+	.bind	= test_manual_bind,
+	.probe	= test_manual_probe,
+	.remove	= test_manual_remove,
+	.unbind	= test_manual_unbind,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 98e3936527..cd2c38995e 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -39,7 +39,8 @@ static int testfdt_ofdata_to_platdata(struct udevice *dev)
 
 	pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					"ping-add", -1);
-	pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+	pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+				      "ping-expect");
 
 	return 0;
 }
@@ -90,55 +91,170 @@ UCLASS_DRIVER(testfdt) = {
 	.id		= UCLASS_TEST_FDT,
 };
 
+int dm_check_devices(struct dm_test_state *dms, int num_devices)
+{
+	struct udevice *dev;
+	int ret;
+	int i;
+
+	/*
+	 * Now check that the ping adds are what we expect. This is using the
+	 * ping-add property in each node.
+	 */
+	for (i = 0; i < num_devices; i++) {
+		uint32_t base;
+
+		ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
+		ut_assert(!ret);
+
+		/*
+		 * Get the 'ping-expect' property, which tells us what the
+		 * ping add should be. We don't use the platdata because we
+		 * want to test the code that sets that up
+		 * (testfdt_drv_probe()).
+		 */
+		base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+				       "ping-expect");
+		debug("dev=%d, base=%d: %s\n", i, base,
+		      fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+
+		ut_assert(!dm_check_operations(dms, dev, base,
+					       dev_get_priv(dev)));
+	}
+
+	return 0;
+}
+
 /* Test that FDT-based binding works correctly */
 static int dm_test_fdt(struct dm_test_state *dms)
 {
-	const int num_drivers = 3;
+	const int num_devices = 4;
 	struct udevice *dev;
 	struct uclass *uc;
 	int ret;
 	int i;
 
-	ret = dm_scan_fdt(gd->fdt_blob);
+	ret = dm_scan_fdt(gd->fdt_blob, false);
 	ut_assert(!ret);
 
 	ret = uclass_get(UCLASS_TEST_FDT, &uc);
 	ut_assert(!ret);
 
-	/* These are num_drivers compatible root-level device tree nodes */
-	ut_asserteq(num_drivers, list_count_items(&uc->dev_head));
+	/* These are num_devices compatible root-level device tree nodes */
+	ut_asserteq(num_devices, list_count_items(&uc->dev_head));
 
 	/* Each should have no platdata / priv */
-	for (i = 0; i < num_drivers; i++) {
+	for (i = 0; i < num_devices; i++) {
 		ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
 		ut_assert(!ret);
 		ut_assert(!dev_get_priv(dev));
 		ut_assert(!dev->platdata);
 	}
 
+	ut_assertok(dm_check_devices(dms, num_devices));
+
+	return 0;
+}
+DM_TEST(dm_test_fdt, 0);
+
+static int dm_test_fdt_pre_reloc(struct dm_test_state *dms)
+{
+	struct uclass *uc;
+	int ret;
+
+	ret = dm_scan_fdt(gd->fdt_blob, true);
+	ut_assert(!ret);
+
+	ret = uclass_get(UCLASS_TEST_FDT, &uc);
+	ut_assert(!ret);
+
+	/* These is only one pre-reloc device */
+	ut_asserteq(1, list_count_items(&uc->dev_head));
+
+	return 0;
+}
+DM_TEST(dm_test_fdt_pre_reloc, 0);
+
+/* Test that sequence numbers are allocated properly */
+static int dm_test_fdt_uclass_seq(struct dm_test_state *dms)
+{
+	struct udevice *dev;
+
+	/* A few basic santiy tests */
+	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 3, true, &dev));
+	ut_asserteq_str("b-test", dev->name);
+
+	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 0, true, &dev));
+	ut_asserteq_str("a-test", dev->name);
+
+	ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 5,
+						       true, &dev));
+	ut_asserteq_ptr(NULL, dev);
+
+	/* Test aliases */
+	ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 6, &dev));
+	ut_asserteq_str("e-test", dev->name);
+
+	ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 7,
+						       true, &dev));
+
 	/*
-	 * Now check that the ping adds are what we expect. This is using the
-	 * ping-add property in each node.
+	 * Note that c-test nodes are not probed since it is not a top-level
+	 * node
 	 */
-	for (i = 0; i < num_drivers; i++) {
-		uint32_t base;
+	ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 3, &dev));
+	ut_asserteq_str("b-test", dev->name);
 
-		ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
-		ut_assert(!ret);
+	/*
+	 * d-test wants sequence number 3 also, but it can't have it because
+	 * b-test gets it first.
+	 */
+	ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev));
+	ut_asserteq_str("d-test", dev->name);
 
-		/*
-		 * Get the 'reg' property, which tells us what the ping add
-		 * should be. We don't use the platdata because we want
-		 * to test the code that sets that up (testfdt_drv_probe()).
-		 */
-		base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
-		debug("dev=%d, base=%d: %s\n", i, base,
-		      fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+	/* d-test actually gets 0 */
+	ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev));
+	ut_asserteq_str("d-test", dev->name);
 
-		ut_assert(!dm_check_operations(dms, dev, base,
-					       dev_get_priv(dev)));
-	}
+	/* initially no one wants seq 1 */
+	ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1,
+						      &dev));
+	ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev));
+	ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 1, &dev));
+
+	/* But now that it is probed, we can find it */
+	ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, &dev));
+	ut_asserteq_str("a-test", dev->name);
 
 	return 0;
 }
-DM_TEST(dm_test_fdt, 0);
+DM_TEST(dm_test_fdt_uclass_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can find a device by device tree offset */
+static int dm_test_fdt_offset(struct dm_test_state *dms)
+{
+	const void *blob = gd->fdt_blob;
+	struct udevice *dev;
+	int node;
+
+	node = fdt_path_offset(blob, "/e-test");
+	ut_assert(node > 0);
+	ut_assertok(uclass_get_device_by_of_offset(UCLASS_TEST_FDT, node,
+						   &dev));
+	ut_asserteq_str("e-test", dev->name);
+
+	/* This node should not be bound */
+	node = fdt_path_offset(blob, "/junk");
+	ut_assert(node > 0);
+	ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT,
+							    node, &dev));
+
+	/* This is not a top level node so should not be probed */
+	node = fdt_path_offset(blob, "/some-bus/c-test@5");
+	ut_assert(node > 0);
+	ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT,
+							    node, &dev));
+
+	return 0;
+}
+DM_TEST(dm_test_fdt_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-main.c b/test/dm/test-main.c
index fbdae688e0..94ce72abfd 100644
--- a/test/dm/test-main.c
+++ b/test/dm/test-main.c
@@ -89,11 +89,11 @@ int dm_test_main(void)
 		ut_assertok(dm_test_init(dms));
 
 		if (test->flags & DM_TESTF_SCAN_PDATA)
-			ut_assertok(dm_scan_platdata());
+			ut_assertok(dm_scan_platdata(false));
 		if (test->flags & DM_TESTF_PROBE_TEST)
 			ut_assertok(do_autoprobe(dms));
 		if (test->flags & DM_TESTF_SCAN_FDT)
-			ut_assertok(dm_scan_fdt(gd->fdt_blob));
+			ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
 
 		if (test->func(dms))
 			break;
diff --git a/test/dm/test.dts b/test/dm/test.dts
index ec5364f7c7..8489595155 100644
--- a/test/dm/test.dts
+++ b/test/dm/test.dts
@@ -6,10 +6,22 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 
+	aliases {
+		console = &uart0;
+		testfdt6 = "/e-test";
+	};
+
+	uart0: serial {
+		compatible = "sandbox,serial";
+		u-boot,dm-pre-reloc;
+	};
+
 	a-test {
 		reg = <0>;
 		compatible = "denx,u-boot-fdt-test";
+		ping-expect = <0>;
 		ping-add = <0>;
+		u-boot,dm-pre-reloc;
 	};
 
 	junk {
@@ -24,23 +36,47 @@
 	b-test {
 		reg = <3>;
 		compatible = "denx,u-boot-fdt-test";
+		ping-expect = <3>;
 		ping-add = <3>;
 	};
 
 	some-bus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reg = <4>;
+		compatible = "denx,u-boot-test-bus";
+		reg = <3>;
+		ping-expect = <4>;
 		ping-add = <4>;
-		c-test {
+		c-test@5 {
 			compatible = "denx,u-boot-fdt-test";
 			reg = <5>;
+			ping-expect = <5>;
 			ping-add = <5>;
 		};
+		c-test@0 {
+			compatible = "denx,u-boot-fdt-test";
+			reg = <0>;
+			ping-expect = <6>;
+			ping-add = <6>;
+		};
+		c-test@1 {
+			compatible = "denx,u-boot-fdt-test";
+			reg = <1>;
+			ping-expect = <7>;
+			ping-add = <7>;
+		};
 	};
 
 	d-test {
-		reg = <6>;
+		reg = <3>;
+		ping-expect = <6>;
+		ping-add = <6>;
+		compatible = "google,another-fdt-test";
+	};
+
+	e-test {
+		reg = <3>;
+		ping-expect = <6>;
 		ping-add = <6>;
 		compatible = "google,another-fdt-test";
 	};
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 4a2d753c21..39a6e8ad5c 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -188,7 +188,8 @@ class BuilderThread(threading.Thread):
         return self.builder.do_make(commit, brd, stage, cwd, *args,
                 **kwargs)
 
-    def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build):
+    def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build,
+                  force_build_failures):
         """Build a particular commit.
 
         If the build is already done, and we are not forcing a build, we skip
@@ -200,6 +201,8 @@ class BuilderThread(threading.Thread):
             work_dir: Directory to which the source will be checked out
             do_config: True to run a make <board>_config on the source
             force_build: Force a build even if one was previously done
+            force_build_failures: Force a bulid if the previous result showed
+                failure
 
         Returns:
             tuple containing:
@@ -215,14 +218,20 @@ class BuilderThread(threading.Thread):
         # Check if the job was already completed last time
         done_file = self.builder.GetDoneFile(commit_upto, brd.target)
         result.already_done = os.path.exists(done_file)
-        if result.already_done and not force_build:
+        will_build = (force_build or force_build_failures or
+            not result.already_done)
+        if result.already_done and will_build:
             # Get the return code from that build and use it
             with open(done_file, 'r') as fd:
                 result.return_code = int(fd.readline())
             err_file = self.builder.GetErrFile(commit_upto, brd.target)
             if os.path.exists(err_file) and os.stat(err_file).st_size:
                 result.stderr = 'bad'
-        else:
+            elif not force_build:
+                # The build passed, so no need to build it again
+                will_build = False
+
+        if will_build:
             # We are going to have to build it. First, get a toolchain
             if not self.toolchain:
                 try:
@@ -411,14 +420,17 @@ class BuilderThread(threading.Thread):
             for commit_upto in range(0, len(job.commits), job.step):
                 result, request_config = self.RunCommit(commit_upto, brd,
                         work_dir, do_config,
-                        force_build or self.builder.force_build)
+                        force_build or self.builder.force_build,
+                        self.builder.force_build_failures)
                 failed = result.return_code or result.stderr
+                did_config = do_config
                 if failed and not do_config:
                     # If our incremental build failed, try building again
                     # with a reconfig.
                     if self.builder.force_config_on_failure:
                         result, request_config = self.RunCommit(commit_upto,
-                            brd, work_dir, True, True)
+                            brd, work_dir, True, True, False)
+                        did_config = True
                 do_config = request_config
 
                 # If we built that commit, then config is done. But if we got
@@ -435,7 +447,7 @@ class BuilderThread(threading.Thread):
                 # Of course this is substantially slower if there are build
                 # errors/warnings (e.g. 2-3x slower even if only 10% of builds
                 # have problems).
-                if (failed and not result.already_done and not do_config and
+                if (failed and not result.already_done and not did_config and
                         self.builder.force_config_on_failure):
                     # If this build failed, try the next one with a
                     # reconfigure.
@@ -498,6 +510,8 @@ class Builder:
         force_config_on_failure: If a commit fails for a board, disable
             incremental building for the next commit we build for that
             board, so that we will see all warnings/errors again.
+        force_build_failures: If a previously-built build (i.e. built on
+            a previous run of buildman) is marked as failed, rebuild it.
         git_dir: Git directory containing source repository
         last_line_len: Length of the last line we printed (used for erasing
             it with new progress information)
@@ -578,6 +592,7 @@ class Builder:
         self._complete_delay = None
         self._next_delay_update = datetime.now()
         self.force_config_on_failure = True
+        self.force_build_failures = False
         self._step = step
 
         self.col = terminal.Color()
diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py
index 73a5483d46..0da6797e7f 100755
--- a/tools/buildman/buildman.py
+++ b/tools/buildman/buildman.py
@@ -72,6 +72,9 @@ parser.add_option('-e', '--show_errors', action='store_true',
 parser.add_option('-f', '--force-build', dest='force_build',
        action='store_true', default=False,
        help='Force build of boards even if already built')
+parser.add_option('-F', '--force-build-failures', dest='force_build_failures',
+       action='store_true', default=False,
+       help='Force build of previously-failed build')
 parser.add_option('-d', '--detail', dest='show_detail',
        action='store_true', default=False,
        help='Show detailed information for each board in summary')
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index d2f4102ba7..cfad535fcb 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -156,6 +156,7 @@ def DoBuildman(options, args):
         ShowActions(series, why_selected, selected, builder, options)
     else:
         builder.force_build = options.force_build
+        builder.force_build_failures = options.force_build_failures
 
         # Work out which boards to build
         board_selected = boards.GetSelectedDict()
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index da7c9f0ddc..1f0fbae8e1 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -77,7 +77,7 @@ int main(int argc, char *argv[])
 {
 	int fd_in, fd_out;
 	struct boot_img img;
-	unsigned file_size, load_size;
+	unsigned file_size;
 	int count;
 
 	if (argc < 2) {
@@ -101,8 +101,6 @@ int main(int argc, char *argv[])
 	if (file_size > SRAM_LOAD_MAX_SIZE) {
 		fprintf(stderr, "ERROR: File too large!\n");
 		return EXIT_FAILURE;
-	} else {
-		load_size = ALIGN(file_size, sizeof(int));
 	}
 
 	fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
@@ -113,8 +111,8 @@ int main(int argc, char *argv[])
 
 	/* read file to buffer to calculate checksum */
 	lseek(fd_in, 0, SEEK_SET);
-	count = read(fd_in, img.code, load_size);
-	if (count != load_size) {
+	count = read(fd_in, img.code, file_size);
+	if (count != file_size) {
 		perror("Reading input image");
 		return EXIT_FAILURE;
 	}
@@ -126,7 +124,7 @@ int main(int argc, char *argv[])
 		 & 0x00FFFFFF);
 	memcpy(img.header.magic, BOOT0_MAGIC, 8);	/* no '0' termination */
 	img.header.length =
-		ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+		ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
 	gen_check_sum(&img.header);
 
 	count = write(fd_out, &img, img.header.length);
author	Stefano Babic <sbabic@denx.de>	2014-08-08 10:18:40 +0200
committer	Stefano Babic <sbabic@denx.de>	2014-08-08 10:18:40 +0200
commit	c23154aab5825fec81d5500c53eaa686646c76b5 (patch)
tree	32b0aafae49f664a65ced50981492bb031f006b8
parent	cb07d74e2e0c0a41533b6bcd551af9bf2ebcf2bc (diff)
parent	9d195a546179bc732aba9eacccf0a9a3db591288 (diff)