Merge branch 'master' of git://git.denx.de/u-boot-arm

11 files changed, 420 insertions, 168 deletions

diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index c4af252110..f8519c0403 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -8,9 +8,12 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
-obj-y	+= keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
 obj-y	+= msmc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-y	+= ddr3.o
+obj-y	+= keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644
index 0000000000..42092e1060
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case DDR3_PLL:
+			ret = external_clk[ddr3_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:      return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
new file mode 100644
index 0000000000..96a9f72886
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = KS2_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:	return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
+	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
+	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6..03c1d9f660 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -8,9 +8,6 @@
  */
 
 #include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
@@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
 	}
 }
 
-struct pll_regs {
-	u32	reg0, reg1;
-};
-
-static const struct pll_regs pll_regs[] = {
-	[CORE_PLL]	= { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
-	[PASS_PLL]	= { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
-	[TETRIS_PLL]	= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
-	[DDR3A_PLL]	= { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
-	[DDR3B_PLL]	= { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
-};
-
-/* Fout = Fref * NF(mult) / NR(prediv) / OD */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(K2HK_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				 PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = K2HK_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = K2HK_ARMPLLCTL0;
-			break;
-		case DDR3A_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = K2HK_DDR3APLLCTL0;
-			break;
-		case DDR3B_PLL:
-			ret = external_clk[ddr3b_clk];
-			reg = K2HK_DDR3BPLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:	return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
-	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
-	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-	return 0;
-}
-
 void init_pll(const struct pll_init_data *data)
 {
 	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
 		tmp = pllctl_reg_read(data->pll, secctl);
 
 		if (tmp & (PLLCTL_BYPASS)) {
-			setbits_le32(pll_regs[data->pll].reg1,
+			setbits_le32(keystone_pll_regs[data->pll].reg1,
 				     BIT(MAIN_ENSAT_OFFSET));
 
 			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
 
 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
 
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
-				(pllm << 6));
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLLM_MULT_HI_SMASK, (pllm << 6));
 
 		/* Set the BWADJ     (12 bit field)  */
 		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_BWADJ_LO_SMASK,
 				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
-		clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+				PLL_BWADJ_HI_MASK,
 				(tmp_ctl >> 8));
 
 		/*
 		 * Set the pll divider (6 bit field) *
 		 * PLLD[5:0] is located in MAINPLLCTL0
 		 */
-		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+				PLL_DIV_MASK, plld);
 
 		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
 		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
 
 		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 
+#ifndef CONFIG_SOC_K2E
 	} else if (data->pll == TETRIS_PLL) {
 		bwadj = pllm >> 1;
 		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
-		setbits_le32(pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
+		setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
 		/*
 		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
-		setbits_le32(pll_regs[data->pll].reg1 ,
+		setbits_le32(keystone_pll_regs[data->pll].reg1 ,
 			     PLL_PLLRST | PLLCTL_ENSAT);
 
 		/*
@@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << 6) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 		/*
 		 * 5 Wait for at least 5 us based on the reference
 		 * clock (PLL reset time)
@@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 
 		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
-		clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
 		/*
 		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
 		 * (PLL lock time)
 		 */
 		sdelay(105000);
 		/* 8 disable bypass */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		/*
 		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
 	} else {
-		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 		/*
 		 * process keeps state of Bypass bit while programming
 		 * all other DDR PLL settings
 		 */
-		tmp = __raw_readl(pll_regs[data->pll].reg0);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
 		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
 
 		/*
@@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
 			(pllm << PLL_MULT_SHIFT) |
 			(plld & PLL_DIV_MASK) |
 			(pllod << PLL_CLKOD_SHIFT);
-		__raw_writel(tmp, pll_regs[data->pll].reg0);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 
 		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 		tmp &= ~(PLL_BWADJ_HI_MASK);
 		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 
@@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
 		if (data->pll == PASS_PLL)
 			tmp |= PLLCTL_PAPLL;
 
-		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 
 		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
 		tmp = PLL_PLLRST;
 		/* Set RESET bit = 1 */
-		setbits_le32(pll_regs[data->pll].reg1, tmp);
+		setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		/* Wait for a minimum of 7 us*/
 		sdelay(21000);
 		/* Clear RESET bit */
-		clrbits_le32(pll_regs[data->pll].reg1, tmp);
+		clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 		sdelay(105000);
 
 		/* clear BYPASS (Enable PLL Mode) */
-		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 		sdelay(21000);	/* Wait for a minimum of 7 us*/
 	}
 
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index afd30f3853..d97c95be11 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -14,10 +14,10 @@
 #include <asm/arch/psc_defs.h>
 
 struct pll_init_data cmd_pll_data = {
-	.pll			= MAIN_PLL,
-	.pll_m			= 16,
-	.pll_d			= 1,
-	.pll_od			= 2,
+	.pll = MAIN_PLL,
+	.pll_m = 16,
+	.pll_d = 1,
+	.pll_od = 2,
 };
 
 int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (strncmp(argv[1], "pa", 2) == 0)
 		cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
 	else if (strncmp(argv[1], "arm", 3) == 0)
 		cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
 	else if (strncmp(argv[1], "ddr3a", 5) == 0)
 		cmd_pll_data.pll = DDR3A_PLL;
 	else if (strncmp(argv[1], "ddr3b", 5) == 0)
 		cmd_pll_data.pll = DDR3B_PLL;
+#else
+	else if (strncmp(argv[1], "ddr3", 4) == 0)
+		cmd_pll_data.pll = DDR3_PLL;
+#endif
 	else
 		goto pll_cmd_usage;
 
@@ -51,11 +58,20 @@ pll_cmd_usage:
 	return cmd_usage(cmdtp);
 }
 
+#ifdef CONFIG_SOC_K2HK
 U_BOOT_CMD(
 	pllset,	5,	0,	do_pll_cmd,
 	"set pll multiplier and pre divider",
 	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
 );
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+	pllset, 5,      0,      do_pll_cmd,
+	"set pll multiplier and pre divider",
+	"<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -79,7 +95,12 @@ U_BOOT_CMD(
 	getclk,	2,	0,	do_getclk_cmd,
 	"get clock rate",
 	"<clk index>\n"
-	"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+	"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+	"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db76a3..2391e794e8 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,11 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <common.h>
+#include <asm/arch/ddr3.h>
 
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
 	unsigned int tmp;
 
@@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 		;
 }
 
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 {
 	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
 	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
 	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
 }
+
+void ddr3_reset_ddrphy(void)
+{
+	u32 tmp;
+
+	/* Assert DDR3A  PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+	writel(tmp, KS2_DDR3APLLCTL1);
+
+	/* wait 10us to catch the reset */
+	udelay(10);
+
+	/* Release DDR3A PHY reset */
+	tmp = readl(KS2_DDR3APLLCTL1);
+	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+	__raw_writel(tmp, KS2_DDR3APLLCTL1);
+}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae..a8f8aee8ab 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,13 +10,14 @@
 #include <common.h>
 #include <ns16550.h>
 #include <asm/io.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 
 void chip_configuration_unlock(void)
 {
-	__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
-	__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
 int arch_cpu_init(void)
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
 	chip_configuration_unlock();
 	icache_enable();
 
-#ifdef CONFIG_SOC_K2HK
-	share_all_segments(8);
-	share_all_segments(9);
-	share_all_segments(10); /* QM PDSP */
-	share_all_segments(11); /* PCIE */
+	msmc_share_all_segments(8);  /* TETRIS */
+	msmc_share_all_segments(9);  /* NETCP */
+	msmc_share_all_segments(10); /* QM PDSP */
+	msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+	msmc_share_all_segments(13); /* PCIE 1 */
 #endif
 
 	/*
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 0000000000..11a9357db4
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,87 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/hardware.h>
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+	u32 i;
+
+	if (!(readl(KS2_DEVSTAT) & 0x1))
+		for (i = 0; i < length; i++, ptr++)
+			*ptr = cpu_to_be32(*ptr);
+
+	return 0;
+}
+
+static int turn_off_myself(void)
+{
+	printf("Turning off ourselves\r\n");
+	mon_power_off(0);
+
+	psc_disable_module(KS2_LPSC_TETRIS);
+	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+	asm volatile ("isb\n"
+		      "dsb\n"
+		      "wfi\n");
+
+	printf("What! Should not see that\n");
+	return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+	int i;
+
+	for (i = 0; i < num_dsps; i++) {
+		if (psc_disable_module(i + KS2_LPSC_GEM_0))
+			printf("Cannot disable module for #%d DSP", i);
+
+		if (psc_disable_domain(i + 8))
+			printf("Cannot disable domain for #%d DSP", i);
+	}
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	return turn_off_myself();
+}
+
+U_BOOT_CMD(
+	killme, 1,      0,      do_killme_cmd,
+	"turn off main ARM core",
+	"turn off main ARM core. Should not live after that :(\n"
+);
+
+int misc_init_r(void)
+{
+	char *env;
+	long ks2_debug = 0;
+
+	env = getenv("ks2_debug");
+
+	if (env)
+		ks2_debug = simple_strtol(env, NULL, 0);
+
+	if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
+		turn_off_all_dsps(KS2_NUM_DSPS);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d20..7d8e5978df 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
 
 struct mpax {
 	u32	mpaxl;
@@ -56,9 +56,9 @@ struct msms_regs {
 };
 
 
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
 {
-	struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
 	int j;
 
 	for (j = 0; j < 8; j++) {
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc84d5..fa5422f2e8 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
 #define DEVICE_REG32_R(addr)			__raw_readl((u32 *)(addr))
 #define DEVICE_REG32_W(addr, val)		__raw_writel(val, (u32 *)(addr))
 
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE				K2HK_PSC_BASE
-#endif
-
 int psc_delay(void)
 {
 	udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
 	retry = 0;
 
 	do {
-		ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+		ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
 		ptstat = ptstat & (1 << domain_num);
 	} while ((ptstat != 0) && ((retry += psc_delay()) <
 		 PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
 	u32 domain_num;
 
 	/* Get the power domain associated with the module number */
-	domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+	domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
 				    PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
 
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * Get the power domain associated with the module number, and reset
 	 * isolation functionality
 	 */
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	domain_num = PSC_REG_MDCFG_GET_PD(v);
 	reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
 
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
 	 * change is made if the new state is power down.
 	 */
 	if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-		pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+		pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
 				       PSC_REG_PDCTL(domain_num));
 		pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
 					       PSC_REG_VAL_PDCTL_NEXT_ON);
-		DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+		DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
 			       pdctl);
 	}
 
 	/* Set the next state for the module to enabled/disabled */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	/* Trigger the enable */
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1<<domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	/* Wait on the complete */
 	return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
 		return 0;
 
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the bit to apply reset */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	if ((mdctl & 0x3f) == 0)
 		return 0;
 	mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
 	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
 	u32 mdctl;
 
 	/* Set the reset isolation bit */
-	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
 	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
 
-	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
 	if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
 		return 0;
 
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
 	u32 pdctl;
 	u32 ptcmd;
 
-	pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+	pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
 	pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
 	pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
 
-	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
 	ptcmd |= (u32)(1 << domain_num);
-	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+	DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
 
 	return psc_wait(domain_num);
 }
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
index e07b64db9e..d4b0e9b163 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -18,10 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_K2HK_EVM
 static struct pll_init_data spl_pll_config[] = {
 	CORE_PLL_799,
 	TETRIS_PLL_500,
 };
+#endif
+
+#ifdef CONFIG_K2E_EVM
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_800,
+};
+#endif
 
 void spl_init_keystone_plls(void)
 {