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path: root/arch/riscv/cpu
AgeCommit message (Expand)Author
2020-07-06Merge branch 'next'Tom Rini
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson
2020-07-01riscv: Clean up IPI initialization codeSean Anderson
2020-07-01riscv: Clear pending interrupts before enabling IPIsSean Anderson
2020-06-04riscv: sifive: fu540: add SPL configurationPragnesh Patel
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel
2020-06-04riscv: Add _image_binary_end for SPLPragnesh Patel
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
2020-05-18common: Drop init.h from common headerSimon Glass
2020-05-18common: Drop net.h from common headerSimon Glass
2020-04-23riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra
2020-04-23riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng
2020-04-23riscv: Merge unnecessary SMP ifdefs in start.SBin Meng
2020-04-23riscv: qemu: Remove the simple-bus driver for the SoC nodeBin Meng
2020-04-23riscv: ax25: cache: Remove SPL_RISCV_MMODE config checkPragnesh Patel
2020-02-10riscv: Remove unnecessary instructionSean Anderson
2020-02-10riscv: Add option to print registers on exceptionSean Anderson
2020-02-10riscv: Fix breakage caused by linker relaxationSean Anderson
2020-01-17common: Move relocate_code() to init.hSimon Glass
2019-12-10riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer
2019-12-10riscv: Fix clear bss loop in the start-up codeRick Chen
2019-12-10riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen
2019-12-10riscv: ax25: add SPL supportRick Chen
2019-12-02common: Move board_get_usable_ram_top() out of common.hSimon Glass
2019-12-02common: Move enable/disable_interrupts out of common.hSimon Glass
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass
2019-09-03riscv: cache: use CCTL to flush d-cacheRick Chen
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen
2019-09-03riscv: update fix_rela_dynMarcus Comstedt
2019-08-26riscv: support SPL stack and global data relocationLukas Auer
2019-08-26riscv: add SPL supportLukas Auer
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-08-15riscv: Access CSRs using CSR numbersBin Meng
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner
2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer
2018-12-18riscv: Save boot hart id to the global dataBin Meng