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Adds a VID specific API in init_sequence_f and spl code flow
namely init_func_vid which is required to adjust core voltage.
VID specific code is required in spl, hence moving flag CONFIG_VID
out of spl flags.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Restructures common driver to support LTC3882 voltage regulator
chip.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Move system flags from defconfig to mach-stm32/Kconfig
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
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Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
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This adds support for '-machine virt' on AArch64. This is rather simple:
we just add TARGET_QEMU_ARM_xxBIT to select a few different Kconfig
symbols, provide the ARMv8 memory map from the board file and add a new
defconfig based on the 32-bit defconfig.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The signing certificate name is always 15 chars long, but need not be
null terminated. One solution is then to use printf precision modifiers
to only print this many chars ("%.15s"), but tiny printf does not support
this, so lets just drop printing the cert name for now.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Fix the size calculation in the verify boot. The header size
should be subtracted from the image size, not be assigned to
the image size.
Fixes: 0830d72bb9f8 ("arm: am33xx: security: adds auth support for encrypted images")
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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This commit adds OMAP3 BeagleBoard devicetree files from
Linux v4.15-rc5. This includes standard OMAP34XX board revisions as
well as the 'xM' which is OMAP36XX.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
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Add initial dts support for am574x-idk
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Enable CMD_DDR3 on all am57xx based platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Update prcm, voltages and pinmux support for am574x-idk.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR@1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs
Both the above packages uses the same IDCODE hence needs to
differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7 platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Move cmd_ddr3 to cmd/ti in order to make
it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Rename to ddr3.c not cmd_ddr3.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
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For data integrity, the EMIF1 supports ECC on the data
written or read from the SDRAM. Add support for enabling
ECC support in EMIF1.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
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This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.
Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Added support for K2G EVM with FlipChip SoC of which
ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also
backward compatible with old revision EVM and EVM
with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s.
The new SoC supports 2 different speeds at 1GHz and 600MHz.
Modyfied the CPU Name to show which SoC is used in the EVM.
Modified the DDR3 configuration to reflect New SoC supports
2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT.
Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz,
and set the u-boot env variable board_name accordingly.
Modified findfdt script in u-boot environment variable to include new k2g board type.
Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance
to use if any at all is done through
CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is
handled in U-boot. Handle this additional pinmuxing requirement in U-boot
to ensure that MCAN is used by default via the DCAN1 pins.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".
Fix it here by using "&= ~()" to reset a bit.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This is useful to make sure no stale data exists in caches after bootloaders.
The worst thing could be some lines of cache were locked in a bootloader
for example during DDR recalibration and never unlocked. This may lead
to really unpredictable issues later down the line.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Add cgu-clk (clock generation unit) node to HSDK device tree.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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We'd like to keep IOC HW at the same state as t is right after reset when we
start Linux kernel so there will be no re-configuration of IOC on the go.
The point is U-Boot doesn't benefit a lot from IOC as it doesn't do a
lot of DMA operations especially on multiple cores simultaneously.
At the same time re-configuration of IOC in run-time might become quite
a tricky experience because we need to make sure there're no DMA
trannsactions in flight otherwise unexpected consequencses might affect
us much later and debugging those kinds of issues will be a real
nightmare.
That said let's make our life easier a little bit.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Previous SLC management implementation is broken. Seems like it was
never sufficiently tested probably because most of the time IOC was used
instead (i.e. no manual cache operations were done).
Now if we disable IOC in U-boot we'll get a lot of errors while using
DMA-enabled peripherals.
This time we fix it by substitution of broken per-line SLC operations
region operations as it is done in the Linux kernel (we took it from
v4.14 which is the latest stable as of today).
Among other things this implementation might be a bit faster because
instead of iteration over each and every cache line we're taking care
about entire region in one go.
Main changes:
* Replaced __slc_line_op (per line operations) by __slc_rgn_op
(region operations).
* Reworked __slc_entire_op to get rid of __after_slc_op and
__before_slc_op functions.
Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is
used, see [1] for more details) is already incorporated here.
* Added SLC invalidation to invalidate_icache_all().
* Added (start >= end) check to invalidate_dcache_range() and
flush_dcache_range() as some buggy drivers pass region start == end.
* Added read-out of MMU BCR so we may know if PAE40 exists in HW and then
act on a particular AUX regs accordingly.
[1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Align the base address defined in header files with the base address used
in the DTS. This will facilitate the introduction of the DMA support.
Of all HSMMC users, only omap3 doesn't have the 0x100 reserved region at
the top. This region will be used to determine if the controller supports
DMA transfers
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This reverts commit 46831c1a4cda75d92f7ad18d4e2b1eb196c62b2f.
This reserved area at the beginning of struct hsmm, will be used later to
support ADMA
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Modify the lpi2c alias seq number to align with device.
Then no need to add 4 to get the device index.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The DT spec demands a unit-address in a node name to match the "reg"
property in that node. Newer dtc versions will throw warnings if this is
not the case.
Remove the unit address from the config node name when U-Boot deals with
secure firmware FIT images.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The DT spec demands a unit-address in a node name to match the "reg"
property in that node. Newer dtc versions will throw warnings if this is
not the case.
Fix all occurences in various documentation files where this was not
observed, to not give bad examples to the reader.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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If lk lights up display and populates simple-framebuffer node, it will
also setup a reserved-memory node (needed by simplefb on linux). But
it isn't clever enough to cope when the reserved-memory node is not
present.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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this should be the norm for armv8 platforms.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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The firmware that runs before u-boot modifies u-boot's device tree
adding the local-mac-address and local-bd-address properties for the
compatibles "qcom,wcnss-bt" and "qcom,wcnss-wlan".
This commit reads that firmware, retrieves the properties and fixups
the device tree that is passed to the kernel before booting.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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This commit adds support for 96Boards Dragonboard820C.
The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.
Features
- 4x Kyro CPU (64 bit) up to 2.15GHz
- USB2.0
- USB3.0
- ISP
- Qualcomm Hexagon DSP
- SD 3.0 (UHS-I)
- UFS 2.0
- Qualcomm Adreno 530 GPU
- GPS
- BT 4.2
- Wi-Fi 2.4GHz, 5GHz (802.11ac)
- PCIe 2.0
- MIPI-CSI, MIPI-DSI
- I2S
U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.
For detailed build instructions see readme.txt in the board directory.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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In preparation to add support for the Dragonboard820c (APQ8096),
refactor the current Snapdragon clock driver.
No new functionality has been added.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII
PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Align boards belonging to LS1012A, LS2080A SoC at one place.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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This is the node that would contain, for example, the framebuffer setup
by an earlier stage.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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hab_failsafe when called puts the part into BootROM recovery mode.
This will allow u-boot scripts to script the dropping down into recovery
mode.
=> hab_failsafe
Shows the i.MX7 appear as "hiddev0,hidraw5: USB HID v1.10 Device [Freescale
SemiConductor Inc SP Blank ULT1] " in a Linux dmesg thus allowing download
of a new image via the BootROM USB download protocol routine.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Breno Matheus Lima <brenomatheus@gmail.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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This patch implements the basic callback hooks for
hab_rvt_check_failsafe for BootROM code using the older BootROM address
layout - in my test case the i.MX7. Code based on new BootROM callbacks
will just do nothing and there's definitely a TODO to implement that extra
functionality on the alternative BootROM API.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Sven Ebenfeld <sven.ebenfeld@gmail.com>
Cc: George McCollister <george.mccollister@gmail.com>
Cc: Breno Matheus Lima <brenomatheus@gmail.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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