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AgeCommit message (Expand)Author
2016-03-17x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese
2016-03-17x86: Add support for the samus chromebookSimon Glass
2016-03-17x86: Support a chained-boot development flowSimon Glass
2016-03-17x86: dts: Drop memory SPD compatible stringSimon Glass
2016-03-17x86: ivybridge: Convert to use the common SDRAM codeSimon Glass
2016-03-17x86: Add common SDRAM-init codeSimon Glass
2016-03-17x86: Move common PCH code into a common placeSimon Glass
2016-03-17arm: Add a 64-bit division routine to the private librarySimon Glass
2016-03-17x86: Add a function to set the IOAPIC IDSimon Glass
2016-03-17x86: broadwell: Add support for high-speed I/O lane with MESimon Glass
2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass
2016-03-17x86: broadwell: Add power-control supportSimon Glass
2016-03-17x86: broadwell: Add reference code supportSimon Glass
2016-03-17x86: broadwell: Add an LPC driverSimon Glass
2016-03-17x86: broadwell: Add a northbridge driverSimon Glass
2016-03-17x86: broadwell: Add a SATA driverSimon Glass
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass
2016-03-17x86: broadwell: Add a PCH driverSimon Glass
2016-03-17x86: Add basic support for broadwellSimon Glass
2016-03-17x86: Add support for running Intel reference codeSimon Glass
2016-03-17x86: Drop all the old pin configuration codeSimon Glass
2016-03-17x86: Add an ICH6 pin configuration driverSimon Glass
2016-03-17x86: link: Add pin configuration to the device treeSimon Glass
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass
2016-03-17x86: Record the CPU details when starting each coreSimon Glass
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass
2016-03-17x86: Allow I/O functions to use pointersSimon Glass
2016-03-17x86: Add macros to clear and set I/O bitsSimon Glass
2016-03-17x86: ivybridge: Drop sandybridge_early_init()Simon Glass
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass
2016-03-17x86: Move common CPU code to its own placeSimon Glass
2016-03-17x86: Move common LPC code to its own placeSimon Glass
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass
2016-03-17x86: Create a common header for Intel register accessSimon Glass
2016-03-17x86: Move microcode code to a common locationSimon Glass
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass
2016-03-17x86: broadwell: Add a few microcode filesSimon Glass
2016-03-17x86: Add comments to the SIPI vectorSimon Glass
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass
2016-03-17x86: Correct duplicate POST valuesSimon Glass
2016-03-17x86: gpio: Correct GPIO setup orderingSimon Glass
2016-03-17x86: dts: link: Add board ID GPIOsSimon Glass
2016-03-17x86: dts: link: Move SPD info into the memory controllerSimon Glass
2016-03-17x86: link: Add required GPIO propertiesSimon Glass
2016-03-17x86: Add some more common MSR indexesSimon Glass
2016-03-17x86: cpu: Make the vendor table constSimon Glass
2016-03-17x86: Support booting SeaBIOSBin Meng