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2020-07-27i2c: mxc: move i2c_early_init_f to common functionBiwen Li
Move i2c_early_init_f to common function to initialize baudrate of i2c Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: add RNG supportMichael Walle
Register the random number generator with the rng subsystem in u-boot. This way it can be used by EFI as well as for the 'rng' command. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: instantiate the RNG with prediciton resistanceMichael Walle
If it is already instantiated tear it down first and then reinstanciate it again with prediction resistance. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: don't regenerate secure keysMichael Walle
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a POR. Otherwise the RNG4 will throw an error. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: support newer SEC modulesMichael Walle
Since Era 10, the version registers changed. Add the version registers and use them on newer modules. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: export caam_get_era()Michael Walle
We need the era in other modules, too. For example, to get the RNG version. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: make SEC%u status line consistentMichael Walle
Align the status line with all the other output in U-Boot. Before the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) After the change: DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on) SEC0: RNG instantiated WDT: Started with servicing (60s timeout) Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: unused value in caam_hash_update()Heinrich Schuchardt
The value 0 assigned to final is overwritten before ever being used. Remove the assignment. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: correct printf() statement.Heinrich Schuchardt
The sequence of arguments should match the format string. For printing unsigned numbers we should use %u. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27Move eSDHC adapter card identification to board filesYangbo Lu
The eSDHC adapter card identification and multiplexing configuration through FPGA had been implemented in both common mmc driver and fsl_esdhc driver. However it is proper to move these code to board files and do it during board initialization. The FPGA registers are also board specific. This patch is to move eSDHC adapter card identification and multiplexing configuration from mmc driver to specific board files. And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27Drop global data sdhc_adapter for powerpcYangbo Lu
The sdhc_adapter of global data has not been used, and we do not have to use it as global data even we may need it in the future. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: ls1012a: RGMII ports require internal delayChaitanya Sakinam
The correct setting for the RGMII ports on LS1012ARDB is to enable delay on both Rx and Tx so the interface mode used should be PHY_INTERFACE_MODE_RGMII_ID Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: fix unaligned accessMichael Walle
On aarch64 running with dcache off, will result in an unaligned access exception: => dcache off => hash sha1 $kernel_addr_r 100 "Synchronous Abort" handler, esr 0x96000061 elr: 00000000960317d8 lr : 00000000960316a4 (reloc) elr: 00000000fbd787d8 lr : 00000000fbd786a4 [..] The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit aligned pointer. Remove the unused u64 element from the union to drop the minimal alignment to 32 bit. Also remove the union, because it is no more needed. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh
Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-24Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24ram: sifive: Avoid using hardcoded ram base and sizeBin Meng
At present the SiFive FU540 RAM driver uses hard-coded memory base address and size to initialize the DDR controller. This may not be true when this driver is used on another board based on FU540. Update the driver to read the memory information from DT and use that during the initialization. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24serial: Fix SIFIVE debug serial dependencyMichal Simek
The commit 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") has added incorrect dependency for SIFIVE debug uart which should depend on SIFIVE driver instead of PL01x. Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Leo Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-07-24sysreset: syscon: Support value propertyBin Meng
Per the DT binding, <mask> and <value> property can have either one or both, and if <value> is missing, <mask> should be used, which is what current U-Boot sysreset_syscon driver supports. This adds support to the <value> property to the driver, and <mask> semantics is updated to really be a mask to the value if both exist. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24sysreset: syscon: Don't assume default value for offset and mask propertyBin Meng
Per the DT binding, <offset> is a required property. Let's abort the probe if it is missing. For the <mask> property, current codes assume a default value of zero, which is not correct either. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-23Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini
binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-22Merge tag 'u-boot-rockchip-20200722' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New rk3326 board: Hardkernel Odroid Go2; - Update board config and dts for RockPI 4/N8/N10; - Update led boot on support for roc-rk3399-pc; - Enable SPI Flash suppor for rk3328 rock64 board; - Update rockchip pcie phy to use generic framework;
2020-07-22pci: rockchip: Drop legacy PHY driverJagan Teki
Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22pci: rockchip: Switch to generic-phyJagan Teki
Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22phy: Add Rockchip PCIe PHY driverJagan Teki
Add the Rockchip PCIe PHY driver as part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang
The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUGJagan Teki
Right now all these debug statements are printing on the console to make sure proper dram initialization happens.   Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful and work like before since the RAM_ROCKCHIP_DEBUG is by default yet. No functionality changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ram: rk3399: Drop debug stride in driverJagan Teki
stride debug is already present in sdram_common.c via RAM_ROCKCHIP_DEBUG. So, drop the redundant debug stride code in rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22drivers: spi: rk_spi: Add support for RK3328Johannes Krottmayer
Add support for the RK3328 SPI controller Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22drivers: clk: rockchip: clk_rk3328: Add SPI supportJohannes Krottmayer
Add SPI support for the RK3328 clock driver Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-20treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20treewide: remove (phys_addr_t) casts from devfdt_get_addr()Masahiro Yamada
This cast is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada
Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCsDave Gerlach
Introduce an soc_ti_k3_driver that allows identification and selection of SoC specific data based on the JTAG ID register for device identification, as described for AM65x[0] and J721E[1] devices. [0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf [1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20test: Add tests for SOC uclassDave Gerlach
Add a sandbox SOC driver, and some tests for the SOC uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach
Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20dm: core Fix long line in device_bind_common()Simon Glass
Fix an over-length line in this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20mtd: spinand: micron: Add new Micron SPI NAND devices with multiple diesShivamurthy Shastri
Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Add M70A series Micron SPI NAND devicesShivamurthy Shastri
Add device table for M70A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Add new Micron SPI NAND devicesShivamurthy Shastri
Add device table for M79A and M78A series Micron SPI NAND devices. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGDShivamurthy Shastri
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20mtd: spinand: micron: Generalize the OOB layout structure and function namesShivamurthy Shastri
In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20dm: core: Don't show an ACPI warning if there is no orderingSimon Glass
Some boards don't care about the ordering of ACPI code fragments. Change the warning to a debug message. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-18sysreset: Add Octeon sysreset driverStefan Roese
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC family. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-17mtd: mtdpart: use uint64_t instead of int for cur_offMartin Kaistra
The types of "offset" and "size" of "struct mtd_partition" are uint64_t, while mtd_parse_partitions() uses int to work with these values. When the offset reaches 2GB, it is interpreted as a negative value, which leads to error messages like mtd: partition "<partition name>" is out of reach -- disabled eg. when using the "ubi part" command. Fix this by using uint64_t for cur_off and cur_sz. Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-07-17treewide: convert bd_t to struct bd_info manuallyMasahiro Yamada
Some code was not converted by coccinelle, somehow. I manually fixed up the remaining, and comments, README docs. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> [trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and include/fdt_support.h] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-17treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
generated by cgit (git 2.34.1) at 2024-12-23 17:30:44 +0000